IPCQ-DMA co-design HW design doc + fix IPCQ slot BW model

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Add hardware design document (docs/ipcq-dma-codesign-hw.md) covering
PE_IPCQ high-level architecture, simulator verification, proposed HW
implementation, and alternatives analysis. Include D2 block diagrams
for baseline and proposed PE architectures.

Fix IPCQ slot-memory bandwidth parameters to match topology.yaml:
SRAM 128→512 GB/s (intrinsic BW, NoC-bottlenecked at 128),
HBM 32→256 GB/s (was per-channel, now per-PE aggregate).

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

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Yangwook Kang

2026-04-28 13:31:02 -07:00

parent 54fcb7e4bc

commit 533e699299

9 changed files with 1121 additions and 6 deletions

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docs/diagrams/pe_proposed.png

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