IPCQ-DMA co-design HW design doc + fix IPCQ slot BW model

Add hardware design document (docs/ipcq-dma-codesign-hw.md) covering
PE_IPCQ high-level architecture, simulator verification, proposed HW
implementation, and alternatives analysis. Include D2 block diagrams
for baseline and proposed PE architectures.

Fix IPCQ slot-memory bandwidth parameters to match topology.yaml:
SRAM 128→512 GB/s (intrinsic BW, NoC-bottlenecked at 128),
HBM 32→256 GB/s (was per-channel, now per-PE aggregate).

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

src/kernbench/common/ipcq_types.py

@@ -37,8 +37,8 @@ class IpcqInvalidDirection(ValueError):
 # and slot read (recv consume). Mirrors topology.yaml component values.
 _BUFFER_KIND_BW: dict[str, tuple[float, float]] = {
     "tcm":  (512.0, 0.0),
-    "sram": (128.0, 2.0),
-    "hbm":  (32.0,  6.0),
+    "sram": (512.0, 2.0),
+    "hbm":  (256.0, 6.0),
 }