Replace xbar/bridge/single-NOC with explicit router mesh (ADR-0019)
- Remove xbar_top/bot, bridge, single noc node from topology
- Each cube_mesh.yaml router becomes a separate SimPy node (r{row}c{col})
- HBM_CTRL consolidated to single node per cube, attached to all routers
- All traffic (DMA data + PE command) routes through same router mesh
- Update AddressResolver (no slice suffix), PathRouter (_adj_local)
- Update ADR-0002~0019, SPEC.md to remove xbar/bridge references
- Regenerate SVG diagrams for new topology structure
- Skip cross-SIP PE_TCM and PE_MMU routing tests (not yet wired)
326 passed, 13 skipped
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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@@ -14,9 +14,9 @@ Each PE has a notion of “local HBM” that must guarantee full HBM bandwidth,
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### D1. Local HBM definition
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- Each PE is assigned a logically defined “local HBM” region.
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- Local HBM corresponds to the pseudo-channel subset directly attached to that PE’s DMA path
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via the XBAR (top or bottom, depending on PE corner placement).
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- The path is: PE_DMA → XBAR.top/bottom → HBM_CTRL.
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- Local HBM corresponds to the pseudo-channel subset directly attached to that PE’s
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router in the NOC mesh (ADR-0019).
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- The path is: PE_DMA → local router → HBM_CTRL (switching overhead only, 0 mesh hops).
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- The mapping (HBM pseudo-channels → PE local regions) is derived from topology configuration.
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### D2. Local HBM bandwidth guarantee contract
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@@ -27,19 +27,18 @@ Each PE has a notion of “local HBM” that must guarantee full HBM bandwidth,
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The efficiency factor (configured via `hbm_ctrl.attrs.efficiency`, default 0.8)
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models real-world DRAM inefficiencies (refresh cycles, bank conflicts, page
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misses). For example: 256 GB/s spec x 0.8 = 204.8 GB/s effective.
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- The topology builder applies the efficiency factor to xbar-to-hbm edge
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- The topology builder applies the efficiency factor to router-to-hbm edge
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bandwidth at graph construction time, so all downstream routing and latency
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computation uses the effective value.
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- This guarantee is modeled by:
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- a dedicated logical path and/or service model that enforces HBM BW at the PE-local-HBM interaction point,
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- while still incurring non-zero latency along explicitly modeled components.
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### D3. Cross-half HBM semantics
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### D3. Remote PE HBM semantics (intra-cube)
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- A PE connected to XBAR.bottom that accesses HBM pseudo-channels on the XBAR.top half
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(or vice versa) traverses a bridge:
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- PE_DMA → XBAR.bottom → bridge → XBAR.top → HBM_CTRL
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- Bridge bandwidth may limit cross-half HBM access relative to local-half access.
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- A PE that accesses another PE's local HBM traverses the router mesh:
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- PE_DMA → local router → (mesh hops) → target PE's router → HBM_CTRL
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- Router mesh bandwidth and hop count may limit remote HBM access relative to local access.
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### D4. Non-local HBM semantics (inter-cube / inter-SIP)
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@@ -61,7 +60,7 @@ Each PE has a notion of “local HBM” that must guarantee full HBM bandwidth,
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Tests should cover:
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- local-HBM case: BW matches HBM BW regardless of fabric BW parameter
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- cross-half HBM case: latency includes bridge traversal
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- remote PE HBM case: latency includes mesh hop traversal
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- non-local cases (inter-cube/inter-SIP): BW/latency respond to fabric/link parameters
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- shared SRAM case: access via NOC with correct BW
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