Add deck builder + overview-with-ref diagram scripts
scripts/build_overview_slides.py renders a 5-slide PPTX (kernbench2_overview.pptx) summarizing architecture, model correctness, IPCQ, allreduce, and buffer-kind tier comparison. scripts/emit_overview_with_external_ref.py renders log-y and broken-y variants of the allreduce overview (overview_log.png, overview_broken.png) including a 366 µs ext-sim reference marker at 96 KB / PE. Also includes cube_mesh_view.png rendered from the SVG. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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"""Generate a 5-slide PPTX summarizing the kernbench2 model.
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Slides (in order):
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1. Overall architecture — how PEs are connected (cube_mesh_view)
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2. Model correctness — DMA vs P2P latency (pe2pe overview)
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3. PE-to-PE IPCQ communication (ipcq_two_pe_dma)
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4. 6-device allreduce — model vs theoretical vs ext-sim (overview_broken)
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5. IPCQ buffer-kind sweep — TCM vs SRAM vs HBM (buffer_kind_sweep)
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This is a derived-artifact generator — no production code touched.
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"""
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from __future__ import annotations
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from pathlib import Path
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from PIL import Image
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from pptx import Presentation
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from pptx.dml.color import RGBColor
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from pptx.enum.shapes import MSO_SHAPE
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from pptx.util import Emu, Inches, Pt
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ROOT = Path(__file__).resolve().parent.parent
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DIAG = ROOT / "docs" / "diagrams"
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OUT = DIAG / "kernbench2_overview.pptx"
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# 16:9 widescreen — 13.333 × 7.5 in
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SLIDE_W_IN = 13.333
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SLIDE_H_IN = 7.5
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SLIDES = [
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{
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"title": "1. CUBE Architecture: NOC Router Mesh + PE Connectivity",
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"image": DIAG / "cube_mesh_view.png",
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"bullets": [
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"Each CUBE holds an 8-PE NOC mesh wired through routers (R0..R7)",
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"Every PE has IO_CPU, M_CPU, PE_CPU + IPCQ engine + DMA engine",
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"Inter-cube traffic exits via UCIe/UAL ports; SIPs stitch into ring/torus/mesh",
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"Foundation for every latency, IPCQ, and allreduce experiment that follows",
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],
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},
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{
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"title": "2. Model Correctness: DMA vs P2P Latency Sweep",
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"image": DIAG / "pe2pe_latency_plots" / "overview.png",
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"bullets": [
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"Sweeps payload size across PE-to-PE paths and compares to DMA",
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"Confirms the simulator reproduces the expected DMA/P2P crossover",
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"Acts as the per-hop ground truth that feeds collective-level models",
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],
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},
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{
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"title": "3. IPCQ: How Two PEs Communicate (DMA + Slot Memory)",
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"image": DIAG / "ipcq_diagram_plots" / "ipcq_two_pe_dma.png",
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"bullets": [
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"Sender pushes payload through PE_DMA → fabric → receiver IPCQ slot",
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"Slot memory (TCM/SRAM/HBM) charges a write on arrival, a read on consume",
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"Credit return rides the fabric path back (16 B packet, no slot-IO)",
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"This is the building block the multi-device allreduce composes",
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],
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},
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{
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"title": "4. 6-Device Allreduce: Model vs Theoretical vs External Simulator",
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"image": DIAG / "allreduce_latency_plots" / "overview_broken.png",
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"bullets": [
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"Three SIP topologies (ring / torus / mesh) swept 16 B → 96 KB per PE",
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"Dashed red curve: hand-derived theoretical model for torus_2d (6 SIPs)",
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"Top panel (broken y-axis): single-device reduce on ext-sim ≈ 366 µs",
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"Our 6-device collective lands at ~17–22 µs — ~17× faster than ext-sim baseline",
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],
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},
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{
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"title": "5. IPCQ Slot Memory: TCM vs SRAM vs HBM",
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"image": DIAG / "allreduce_latency_plots" / "buffer_kind_sweep.png",
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"bullets": [
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"Same allreduce with slot memory swapped: TCM (per-PE local) / SRAM / HBM (cube-shared, behind router link)",
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"Cost = NoC drain + slot-IO + PE↔bank hop; only TCM skips the bank hop",
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"Topology link BWs set the order: SRAM bank link 128 GB/s is the narrowest in the system, HBM 256 GB/s",
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"At 64 KB / PE: TCM 12.0 µs < HBM 21.4 µs < SRAM 24.3 µs — SRAM is slowest because of its narrow bank link",
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],
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},
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]
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def _add_title(slide, text):
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left = Inches(0.4)
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top = Inches(0.25)
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width = Inches(SLIDE_W_IN - 0.8)
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height = Inches(0.7)
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box = slide.shapes.add_textbox(left, top, width, height)
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tf = box.text_frame
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tf.margin_left = tf.margin_right = Emu(0)
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tf.margin_top = tf.margin_bottom = Emu(0)
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p = tf.paragraphs[0]
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run = p.add_run()
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run.text = text
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run.font.size = Pt(26)
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run.font.bold = True
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run.font.color.rgb = RGBColor(0x10, 0x2A, 0x55)
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return box
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def _add_image_centered(slide, img_path, *, left_in, top_in, max_w_in, max_h_in):
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with Image.open(img_path) as im:
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iw, ih = im.size
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max_w_emu = Inches(max_w_in)
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max_h_emu = Inches(max_h_in)
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scale = min(max_w_emu / iw, max_h_emu / ih)
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w = int(iw * scale)
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h = int(ih * scale)
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left = Inches(left_in) + (max_w_emu - w) // 2
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top = Inches(top_in) + (max_h_emu - h) // 2
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slide.shapes.add_picture(str(img_path), left, top, width=w, height=h)
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def _add_bullets(slide, bullets, *, left_in, top_in, width_in, height_in):
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box = slide.shapes.add_textbox(
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Inches(left_in), Inches(top_in), Inches(width_in), Inches(height_in),
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)
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tf = box.text_frame
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tf.word_wrap = True
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for i, line in enumerate(bullets):
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p = tf.paragraphs[0] if i == 0 else tf.add_paragraph()
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p.level = 0
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run = p.add_run()
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run.text = "• " + line
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run.font.size = Pt(15)
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run.font.color.rgb = RGBColor(0x22, 0x22, 0x22)
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p.space_after = Pt(6)
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def _add_footer(slide, idx, total):
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box = slide.shapes.add_textbox(
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Inches(SLIDE_W_IN - 1.2), Inches(SLIDE_H_IN - 0.45),
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Inches(1.0), Inches(0.3),
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)
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p = box.text_frame.paragraphs[0]
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run = p.add_run()
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run.text = f"{idx} / {total}"
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run.font.size = Pt(10)
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run.font.color.rgb = RGBColor(0x88, 0x88, 0x88)
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def build():
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prs = Presentation()
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prs.slide_width = Inches(SLIDE_W_IN)
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prs.slide_height = Inches(SLIDE_H_IN)
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blank = prs.slide_layouts[6]
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for i, cfg in enumerate(SLIDES, start=1):
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slide = prs.slides.add_slide(blank)
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_add_title(slide, cfg["title"])
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# Layout: image on the left (8.4 in wide), bullets on the right (4.4 in).
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_add_image_centered(
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slide, cfg["image"],
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left_in=0.3, top_in=1.05,
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max_w_in=8.3, max_h_in=5.9,
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)
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_add_bullets(
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slide, cfg["bullets"],
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left_in=8.8, top_in=1.2,
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width_in=4.3, height_in=5.7,
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)
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_add_footer(slide, i, len(SLIDES))
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OUT.parent.mkdir(parents=True, exist_ok=True)
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prs.save(OUT)
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print(f"wrote {OUT}")
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if __name__ == "__main__":
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build()
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