Add SIP-level tensor parallelism, component registry YAML, VA offset verification

- DPPolicy: 3-level (sip/cube/pe), unified naming (column_wise/row_wise)
- PE_CPU: auto num_programs from cube shard count
- context.launch(): per-SIP KernelLaunchMsg with local va_base + auto local shape
- deploy_tensor: removed mmus param, MMU mapping is context-only responsibility
- ComponentRegistry: YAML-based lazy loading (components.yaml), impls→builtin rename
- VA offset bench + tests: 2D/1D, standard Triton kernel pattern

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

docs/adr/ADR-0011-memory-addressing-simplification.md

@@ -58,7 +58,7 @@ sufficient to execute kernels and issue DMA requests.
 - Mapping strategy based on `DPPolicy.cube`:
   - **Replicate** (`cube="replicate"`): per-(sip, cube) local mapping only.
     Each cube's PEs see only their local PA. No cross-cube mapping installed.
-  - **Sharded** (`cube="shard_m"`, etc.): broadcast all shard mappings to all
+  - **Sharded** (`cube="column_wise"`, etc.): broadcast all shard mappings to all
     target cubes. Enables cross-PE and cross-cube DMA.
 
 #### D3.4 Tensor Lifecycle