Add SIP-level tensor parallelism, component registry YAML, VA offset verification

- DPPolicy: 3-level (sip/cube/pe), unified naming (column_wise/row_wise)
- PE_CPU: auto num_programs from cube shard count
- context.launch(): per-SIP KernelLaunchMsg with local va_base + auto local shape
- deploy_tensor: removed mmus param, MMU mapping is context-only responsibility
- ComponentRegistry: YAML-based lazy loading (components.yaml), impls→builtin rename
- VA offset bench + tests: 2D/1D, standard Triton kernel pattern

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

tests/test_phase_a_components.py

@@ -19,7 +19,7 @@ import simpy
 
 from kernbench.components.base import ComponentBase, ComponentRegistry
 from kernbench.components.context import ComponentContext
-from kernbench.components.impls import (
+from kernbench.components.builtin import (
     HbmCtrlComponent,
     IoCpuComponent,
     MCpuComponent,