paper: §2 platform deep-edit + §1 GQA framing + figure regen

§2 (KernBench Platform):
- Fix Table 2 HBM aggregate BW (1024 → 2048 GB/s); drop stale
  hbm_total_bw_gbs from topology.yaml (never read by sim_engine)
- Split PE_CPU / PE_SCHED fixed-cost row; disambiguate from the
  40-cycle command-dispatch FIXED term
- §2.2 two-pass: expand to describe Pass 1 timing and Pass 2 data
  data-correctness path
- §2.3 dispatch model: add motivation sentence for the
  descriptor-size linear form
- §2.4 Accuracy: reorder GEMM → All-reduce → Probe →
  Simplifications; drop FSIM aside (already covered by §4 Fig 5
  caption); soften 'every ns' → 'every modeled latency
  contribution'
- §2.5 HW config: add 64 TFLOP/s vs 2048 GB/s (~31 FLOP/byte)
  balance-point intuition and forward pointer to §5 GQA decode
- Fig 1 caption: separate illustrative topology from experimental
  configuration

§1: tighten GQA-as-primary-bandwidth-bottleneck framing.

Figures: regenerate SIP / CUBE architecture (SVG sources + PDF +
generator scripts).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

topology.yaml

@@ -98,7 +98,6 @@ cube:
   memory_map:
     hbm_total_gb_per_cube: 48
     hbm_slices_per_cube: 8
-    hbm_total_bw_gbs: 1024.0
     hbm_mapping_mode: n_to_one        # one_to_one | n_to_one (ADR-0017 D8)
     hbm_pseudo_channels: 64           # total pseudo channels per cube
     hbm_channels_per_pe: 8            # = pseudo_channels / pes_per_cube