ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
Remove rack_id (4 bits), rename sip_seg→die_id, shift fields to enable 42-bit local_offset (4 TB per die). Define PE_LOCAL/MCPU_LOCAL/CUBE_SRAM sub-unit tables for AHBM dies and IOCPU sub-unit table for IOCHIPLET dies (1 TB window). Supersedes ADR-0031. Also fixes latent VA/PA confusion in pe_dma pipeline DMA path where virtual addresses were decoded as physical addresses without MMU translation — previously masked by coincidental bit-position alignment. 529 passed (+6 recovered), 10 pre-existing failures unchanged. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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@@ -220,10 +220,10 @@ class IoCpuComponent(ComponentBase):
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return []
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def _cube_from_pa(self, pa_val: int, fallback: int) -> int:
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"""Extract cube_id from a physical address, with fallback."""
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"""Extract die_id from a physical address, with fallback."""
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from kernbench.policy.address.phyaddr import PhysAddr
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try:
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return PhysAddr.decode(pa_val).cube_id
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return PhysAddr.decode(pa_val).die_id
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except Exception:
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return fallback
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@@ -302,7 +302,16 @@ class PeDmaComponent(PeEngineBase):
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dma_res = self._dma_write if is_write else self._dma_read
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assert dma_res is not None
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pa = PhysAddr.decode(addr)
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# Translate VA → PA via MMU (same logic as non-pipeline path)
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target_pa = addr
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if self._mmu is not None:
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from kernbench.policy.address.pe_mmu import PageFault
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try:
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target_pa = self._mmu.translate(addr)
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except PageFault:
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target_pa = addr # fallback: treat as PA directly
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pa = PhysAddr.decode(target_pa)
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dst_node = self.ctx.resolver.resolve(pa)
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path = self.ctx.router.find_path(self._pe_prefix, dst_node)
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drain_ns = self.ctx.compute_drain_ns(path, nbytes)
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@@ -314,7 +323,7 @@ class PeDmaComponent(PeEngineBase):
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correlation_id="pipeline",
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request_id=f"tile_{token.tile_id}",
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src_sip=0, src_cube=0, src_pe=0,
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dst_pa=addr, nbytes=nbytes,
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dst_pa=target_pa, nbytes=nbytes,
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is_write=is_write,
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)
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sub_txn = Transaction(
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