ADR-0023 D9.7: IPCQ slot-memory latency model (TCM/SRAM/HBM)
Charge per-tier bandwidth + setup overhead at IPCQ slot WRITE
(receiver inbound DMA, in pe_dma._handle_ipcq_inbound) and slot
READ (recv consume, in pe_ipcq._handle_recv). Tier table
(common/ipcq_types.py):
tcm : 512 GB/s, 0 ns
sram : 128 GB/s, 2 ns
hbm : 32 GB/s, 6 ns
Before this change, slot read/write was free regardless of
buffer_kind, making memory-tier choice invisible in simulated
latency. After the change, swapping buffer_kind in ccl.yaml
produces measurable per-tier separation in allreduce latency.
Tests:
test_ipcq_buffer_kind_latency.py — three micro-tests asserting
tcm < sram < hbm ordering, payload-scaling, and that
buffer_kind sensitivity grows with payload (credit-only path
stays fabric-bound).
test_allreduce_buffer_kind_sweep.py — 12-config parametrized
sweep emitting buffer_kind_sweep.png (3 lines, torus_2d).
conftest sessionfinish hook generalised to dispatch multiple
sweep aggregators (allreduce + buffer-kind).
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
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"""Phase 1 micro-tests for IPCQ slot-memory latency model.
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These tests assert the TARGET behavior expected after Phase 2 wires
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``buffer_kind`` (tcm/sram/hbm) into the IPCQ slot read/write latency
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charges. They are written BEFORE the production change and are
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EXPECTED TO FAIL today.
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Failure semantics today:
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- Slot access is latency-free, so the tcm/sram/hbm runs produce
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identical pe_exec_ns. The ordering assertion therefore fails with
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"tcm == sram == hbm" — proving the test harness is wired and that
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Phase 2 production work is what makes them pass.
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Reference (Phase 2 will edit these):
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- src/kernbench/components/builtin/pe_dma.py — _handle_ipcq_inbound
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- src/kernbench/components/builtin/pe_ipcq.py — _handle_recv,
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_BUFFER_KIND_BW table
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- src/kernbench/runtime_api/kernel.py — IpcqDmaToken adds
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buffer_kind field
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- ccl.yaml — algorithm.buffer_kind
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The tests reuse the existing config-driven allreduce app
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(``run_allreduce`` in tests/test_allreduce_multidevice.py) with a 2-SIP
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ring topology and a SMALL n_elem so they finish fast (~3-5 s each).
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"""
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from __future__ import annotations
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from pathlib import Path
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from typing import Any
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import pytest
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from kernbench.runtime_api.context import RuntimeContext
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from kernbench.runtime_api.types import DeviceSelector
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from kernbench.sim_engine.engine import GraphEngine
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from kernbench.topology.builder import resolve_topology
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# Reuse the test app's helpers so this micro-test file does not
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# duplicate the run-allreduce + write-temp-configs plumbing.
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from tests.test_allreduce_multidevice import (
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_write_temp_configs,
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run_allreduce,
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)
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# Expected per-tier BW + overhead (Phase 2 will encode this in
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# pe_ipcq.py). Mirrors topology.yaml component values.
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_EXPECTED_BW = {
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"tcm": (512.0, 0.0),
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"sram": (128.0, 2.0),
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"hbm": (32.0, 6.0),
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}
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def _expected_slot_io_ns(buffer_kind: str, nbytes: int) -> float:
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"""Per-access latency the model is expected to add (write OR read)."""
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bw_gbs, overhead_ns = _EXPECTED_BW[buffer_kind]
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# 1 GB/s = 1 byte/ns
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return nbytes / bw_gbs + overhead_ns
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def _run_torus_allreduce(
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tmp_path: Path, *, buffer_kind: str, n_elem: int,
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) -> float:
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"""Run one torus_2d 6-SIP allreduce and return critical-path
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pe_exec_ns. The buffer_kind override is wired into ccl.yaml.
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"""
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sub = tmp_path / f"{buffer_kind}_{n_elem}"
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sub.mkdir()
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topo_path, ccl_path = _write_temp_configs(
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sub,
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sip_topology="torus_2d",
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n_sips=6,
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algorithm="intercube_allreduce",
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sip_w=3, sip_h=2,
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n_elem_override=n_elem,
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)
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# Patch ccl.yaml in-place so the algorithm picks up buffer_kind.
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import yaml
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with open(ccl_path) as f:
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ccl_cfg = yaml.safe_load(f)
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ccl_cfg.setdefault("defaults", {})["buffer_kind"] = buffer_kind
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ccl_cfg.setdefault("algorithms", {}).setdefault(
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"intercube_allreduce", {},
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)["buffer_kind"] = buffer_kind
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with open(ccl_path, "w") as f:
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yaml.dump(ccl_cfg, f, default_flow_style=False)
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topo = resolve_topology(topo_path)
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engine = GraphEngine(topo.topology_obj, enable_data=True)
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spec = topo.topology_obj.spec
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with RuntimeContext(
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engine=engine,
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target_device=DeviceSelector("all"),
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correlation_id=f"bk_{buffer_kind}_{n_elem}",
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spec=spec,
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) as ctx:
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result = run_allreduce(
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ctx, engine, spec,
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algorithm="intercube_allreduce", ccl_yaml=ccl_path,
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)
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assert result["ok_cubes"] > 0, "allreduce did not validate"
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pe_exec_vals = [
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float(tr.get("pe_exec_ns", 0.0) or 0.0)
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for _, (_, tr) in engine._results.items()
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if isinstance(tr, dict)
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]
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return max(pe_exec_vals) if pe_exec_vals else 0.0
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# ── Phase 1 assertions ───────────────────────────────────────────────
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def test_slot_write_latency_orders_tcm_sram_hbm(tmp_path):
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"""tcm < sram < hbm at 8192 B per send.
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Pre-Phase-2: all three return the same pe_exec_ns and this
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assertion fails. Post-Phase-2: the per-tier BW + overhead make
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hbm visibly slower than sram, which is slower than tcm.
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"""
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n_elem = 4096 # 8192 B per slot
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lat_tcm = _run_torus_allreduce(tmp_path, buffer_kind="tcm", n_elem=n_elem)
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lat_sram = _run_torus_allreduce(tmp_path, buffer_kind="sram", n_elem=n_elem)
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lat_hbm = _run_torus_allreduce(tmp_path, buffer_kind="hbm", n_elem=n_elem)
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# Expected per-access deltas (write+read = 2× the per-access value).
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exp_tcm = 2 * _expected_slot_io_ns("tcm", n_elem * 2)
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exp_sram = 2 * _expected_slot_io_ns("sram", n_elem * 2)
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exp_hbm = 2 * _expected_slot_io_ns("hbm", n_elem * 2)
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# Floor margin: 50% of the raw expected per-access delta — lets Phase 2
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# implementation choose to charge only one side without breaking the test,
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# but still requires a clearly observable gap.
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margin_sram_tcm = 0.5 * (exp_sram - exp_tcm)
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margin_hbm_sram = 0.5 * (exp_hbm - exp_sram)
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assert lat_sram > lat_tcm + margin_sram_tcm, (
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f"sram should be slower than tcm by ≥ {margin_sram_tcm:.1f} ns "
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f"per allreduce, got sram={lat_sram:.1f} tcm={lat_tcm:.1f} "
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f"(delta={lat_sram - lat_tcm:.1f})"
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)
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assert lat_hbm > lat_sram + margin_hbm_sram, (
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f"hbm should be slower than sram by ≥ {margin_hbm_sram:.1f} ns "
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f"per allreduce, got hbm={lat_hbm:.1f} sram={lat_sram:.1f} "
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f"(delta={lat_hbm - lat_sram:.1f})"
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)
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def test_slot_io_scales_linearly_with_nbytes(tmp_path):
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"""For buffer_kind=hbm, doubling nbytes should add ~nbytes/32 ns
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of latency to each slot access. Sanity-checks the slope.
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Pre-Phase-2: latency does not respond to nbytes via memory BW
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(only via fabric drain), so the observed slope is dominated by
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fabric BW and does NOT match 1/32 ns/B.
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"""
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lat_4k = _run_torus_allreduce(tmp_path, buffer_kind="hbm", n_elem=2048)
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lat_8k = _run_torus_allreduce(tmp_path, buffer_kind="hbm", n_elem=4096)
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# Expected delta from doubling: at least one slot-IO event per cube
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# in the critical path (very conservative). Per-access add = 4096/32 ≈ 128
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# ns on HBM going from 4k → 8k. Multiple slot accesses on the critical
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# path should make the observed delta meaningfully larger.
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expected_min_delta = 0.5 * (4096 / 32.0) # ≈ 64 ns
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assert lat_8k - lat_4k > expected_min_delta, (
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f"doubling nbytes on hbm should add ≥ {expected_min_delta:.1f} ns "
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f"of slot-IO latency, got delta={lat_8k - lat_4k:.1f} ns "
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f"(lat_4k={lat_4k:.1f}, lat_8k={lat_8k:.1f})"
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)
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def test_buffer_kind_sensitivity_grows_with_payload(tmp_path):
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"""Credit-return cost is fabric-only by design (16 B packet); only
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the data slot-IO charge depends on ``buffer_kind``. Therefore the
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tcm-vs-hbm gap must scale with payload size and be a small fraction
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of the large-payload gap at small payloads.
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Concrete invariant the model must satisfy:
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gap_small / gap_large < 0.10
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Pre-Phase-2: gap_small == gap_large == 0 (division undefined → test
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fails because gap_large is required > 0). Post-Phase-2: at small
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nbytes the slot-IO charge is dominated by the constant
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``overhead_ns`` term, while at large nbytes it is dominated by the
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``nbytes / bw_gbs`` term — so gap_large grows linearly while
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gap_small stays small.
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"""
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n_elem_small = 8 # 16 B per slot — overhead-bound
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n_elem_large = 16384 # 32 KB per slot — bandwidth-bound
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lat_tcm_small = _run_torus_allreduce(
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tmp_path, buffer_kind="tcm", n_elem=n_elem_small,
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)
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lat_hbm_small = _run_torus_allreduce(
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tmp_path, buffer_kind="hbm", n_elem=n_elem_small,
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)
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lat_tcm_large = _run_torus_allreduce(
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tmp_path, buffer_kind="tcm", n_elem=n_elem_large,
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)
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lat_hbm_large = _run_torus_allreduce(
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tmp_path, buffer_kind="hbm", n_elem=n_elem_large,
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)
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gap_small = abs(lat_hbm_small - lat_tcm_small)
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gap_large = abs(lat_hbm_large - lat_tcm_large)
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assert gap_large > 1000.0, (
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f"large-payload buffer_kind gap must be observably large "
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f"(this is the sweep's whole point). got gap_large={gap_large:.1f} ns "
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f"(lat_tcm_large={lat_tcm_large:.1f}, lat_hbm_large={lat_hbm_large:.1f})"
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)
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assert gap_small / gap_large < 0.10, (
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f"buffer_kind sensitivity should grow with payload — "
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f"small-payload gap should be < 10% of large-payload gap. "
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f"got gap_small={gap_small:.1f} ns, gap_large={gap_large:.1f} ns, "
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f"ratio={gap_small / gap_large:.3f}"
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)
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