Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)

Major changes:

PE-level IPCQ infrastructure:
- New PE_IPCQ component: ring-buffer control plane with 4-direction
  neighbor mapping, head/tail pointers, backpressure (poll/sleep).
- PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA,
  including in-flight data snapshot (D9) and op_log recording at
  outbound time for Phase 2 replay correctness.
- IpcqDmaToken piggyback model: data + metadata travel together,
  atomic visibility at receiver (invariant I6).
- Credit return fast path: bottleneck-BW latency, no fabric vc_comm.

Phase 2 data execution (ADR-0020 integration):
- op_log extended: DmaWriteCmd now captures src_space/src_addr for
  Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time.
- DataExecutor replays dma_write + ipcq_copy in t_start order.
- Engine._flush_data_phase: incremental cursor-based replay after
  each engine.wait() so host reads see post-Phase-2 data.
- KernelRunner Phase 1 writes disabled when op_log is active to
  prevent stale data from corrupting the MemoryStore snapshot.

TLContext / kernel API:
- tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype),
  tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode.
- TensorHandle operator overloading (add/sub/mul/div) via thread-local
  active TLContext → MathCmd dispatch through PE_MATH.
- PE-local scratch allocator for math output handles.
- tl.load returns space="hbm" handles for correct Phase 2 addressing.
- Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv.

Unified ccl_allreduce bench (PyTorch-compat host code):
- Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch)
  split matching real PyTorch DDP worker pattern.
- torch.distributed facade: init_process_group, get_world_size,
  get_rank, get_backend, all_reduce, barrier — only real PyTorch names.
- AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches
  kernel via tensor shard metadata (n_elem from shards[0].nbytes).
- world_size derived from topology spec (sips × cubes × pes_per_cube)
  with optional algorithm-level override in ccl.yaml.

Tensor API (PyTorch-compat surface):
- Tensor.numpy(): gather-aware (all shards via VA-based addressing).
- Tensor.copy_(source): scatter from host tensor into sharded target.
- RuntimeContext.from_numpy(arr): host-side staging tensor.
- Tensor.data property fixed to use numpy() (was shards[0]-only).

Algorithm modules moved to src/kernbench/ccl/algorithms/:
- ring_allreduce, mesh_allreduce, tree_allreduce, hello_send.
- Each module exports kernel_args(world_size, n_elem) helper.
- ccl.yaml module paths updated to kernbench.ccl.algorithms.*.

Dead code removed:
- 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.).
- _run_ccl_bench greenlet-per-SIP scheduler.
- benches.loader.is_ccl_bench + run_rank detection.
- benches/ccl/ directory.

Tests:
- New test_ccl_allreduce_matrix.py: 7 parametrized cases
  (ring×3 buffers, ring 8/16, mesh 4, tree 7).
- New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests.
- Existing tests updated for new import paths + world_size_override.

Docs:
- Korean ccl-author-guide.md and ADR-0023 paths updated.
- New English versions: ccl-author-guide.en.md, ADR-0023.en.md.

502 tests pass.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

src/kernbench/sim_engine/engine.py

@@ -51,8 +51,12 @@ class GraphEngine:
         if enable_data:
             from kernbench.sim_engine.memory_store import MemoryStore
             from kernbench.sim_engine.op_log import OpLogger
-            self._op_logger = OpLogger()
             self._memory_store = MemoryStore()
+            self._op_logger = OpLogger(memory_store=self._memory_store)
+        # Cursor for incremental Phase 2 replay (ADR-0020 D6).
+        # SimPy env.now is monotonic so newly logged records always sort
+        # to the tail; the cursor remains valid across waits.
+        self._data_cursor = 0
 
         ctx = ComponentContext(
             router=self._router,
@@ -147,11 +151,60 @@ class GraphEngine:
         self._env.process(self._process(str(handle), request, event))
         return handle
 
+    def _flush_data_phase(self) -> None:
+        """Replay newly recorded op_log entries through DataExecutor.
+
+        ADR-0020 D6 Phase 2: when data tracking is enabled, run DataExecutor
+        on records added since the last flush so that callers reading
+        MemoryStore between launches observe correct (compute-replayed)
+        tensor data.
+
+        Cursor-based incremental replay is necessary because Phase 2 is
+        NOT idempotent across full re-runs: a math op writes a TCM scratch
+        addr, a later dma_write copies that scratch into HBM[X], and an
+        even-later math op may then read HBM[X]. Re-running everything
+        from scratch would let the second pass's first math op read the
+        already-overwritten HBM[X] instead of the original input.
+        """
+        if self._op_logger is None or self._memory_store is None:
+            return
+        records = self._op_logger.records  # sorted by t_start (stable)
+        if self._data_cursor >= len(records):
+            return
+        new_records = records[self._data_cursor:]
+        from kernbench.sim_engine.data_executor import DataExecutor
+        DataExecutor(new_records, self._memory_store).run()
+        self._data_cursor = len(records)
+
     def wait(self, handle: RequestHandle) -> None:
         key = str(handle)
         event = self._events[key]
         if not event.triggered:
-            self._env.run(until=event)
+            try:
+                self._env.run(until=event)
+            except (simpy.core.EmptySchedule, RuntimeError) as exc:
+                # SimPy raises EmptySchedule directly OR (in newer simpy)
+                # wraps it as a RuntimeError("No scheduled events left ...").
+                # Either case while our event is still pending → IPCQ deadlock.
+                msg = str(exc)
+                is_deadlock = (
+                    isinstance(exc, simpy.core.EmptySchedule)
+                    or "No scheduled events left" in msg
+                )
+                if not is_deadlock:
+                    raise
+                from kernbench.ccl.diagnostics import IpcqDeadlock, pointer_dump
+                dump = pointer_dump(self)
+                if dump.strip():
+                    raise IpcqDeadlock(
+                        "IPCQ deadlock: simulation schedule empty while "
+                        f"request {handle!r} is still pending.\n"
+                        f"Pointer state:\n{dump}"
+                    ) from None
+                raise
+        # ADR-0020: replay newly logged ops so the caller observes
+        # post-Phase-2 tensor state from MemoryStore.
+        self._flush_data_phase()
 
     def get_completion(self, handle: RequestHandle) -> tuple[Completion, Trace | None]:
         return self._results[str(handle)]