Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)

Major changes: PE-level IPCQ infrastructure: - New PE_IPCQ component: ring-buffer control plane with 4-direction neighbor mapping, head/tail pointers, backpressure (poll/sleep). - PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA, including in-flight data snapshot (D9) and op_log recording at outbound time for Phase 2 replay correctness. - IpcqDmaToken piggyback model: data + metadata travel together, atomic visibility at receiver (invariant I6). - Credit return fast path: bottleneck-BW latency, no fabric vc_comm. Phase 2 data execution (ADR-0020 integration): - op_log extended: DmaWriteCmd now captures src_space/src_addr for Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time. - DataExecutor replays dma_write + ipcq_copy in t_start order. - Engine._flush_data_phase: incremental cursor-based replay after each engine.wait() so host reads see post-Phase-2 data. - KernelRunner Phase 1 writes disabled when op_log is active to prevent stale data from corrupting the MemoryStore snapshot. TLContext / kernel API: - tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype), tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode. - TensorHandle operator overloading (add/sub/mul/div) via thread-local active TLContext → MathCmd dispatch through PE_MATH. - PE-local scratch allocator for math output handles. - tl.load returns space="hbm" handles for correct Phase 2 addressing. - Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv. Unified ccl_allreduce bench (PyTorch-compat host code): - Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch) split matching real PyTorch DDP worker pattern. - torch.distributed facade: init_process_group, get_world_size, get_rank, get_backend, all_reduce, barrier — only real PyTorch names. - AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches kernel via tensor shard metadata (n_elem from shards[0].nbytes). - world_size derived from topology spec (sips × cubes × pes_per_cube) with optional algorithm-level override in ccl.yaml. Tensor API (PyTorch-compat surface): - Tensor.numpy(): gather-aware (all shards via VA-based addressing). - Tensor.copy_(source): scatter from host tensor into sharded target. - RuntimeContext.from_numpy(arr): host-side staging tensor. - Tensor.data property fixed to use numpy() (was shards[0]-only). Algorithm modules moved to src/kernbench/ccl/algorithms/: - ring_allreduce, mesh_allreduce, tree_allreduce, hello_send. - Each module exports kernel_args(world_size, n_elem) helper. - ccl.yaml module paths updated to kernbench.ccl.algorithms.*. Dead code removed: - 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.). - _run_ccl_bench greenlet-per-SIP scheduler. - benches.loader.is_ccl_bench + run_rank detection. - benches/ccl/ directory. Tests: - New test_ccl_allreduce_matrix.py: 7 parametrized cases (ring×3 buffers, ring 8/16, mesh 4, tree 7). - New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests. - Existing tests updated for new import paths + world_size_override. Docs: - Korean ccl-author-guide.md and ADR-0023 paths updated. - New English versions: ccl-author-guide.en.md, ADR-0023.en.md. 502 tests pass. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
2026-04-12 19:36:59 -07:00
parent ff2c677a9c
commit 998cc85762
60 changed files with 9196 additions and 80 deletions
@@ -0,0 +1,140 @@
+"""Tests for IPCQ strict shape/dtype validation (ADR-0023 D14 F2)."""
+from __future__ import annotations
+
+from dataclasses import dataclass, field
+from typing import Any
+
+import pytest
+import simpy
+
+from kernbench.common.ipcq_types import (
+    IpcqDmaToken,
+    IpcqEndpoint,
+    IpcqInitEntry,
+    IpcqInvalidDirection,
+    IpcqMetaArrival,
+    IpcqRecvCmd,
+    IpcqRequest,
+    IpcqSendCmd,
+)
+from kernbench.components.builtin.pe_ipcq import PeIpcqComponent
+from kernbench.runtime_api.kernel import IpcqInitMsg
+from kernbench.topology.types import Node
+
+
+# ── helpers (smaller copy of test_pe_ipcq fixtures) ────────────────
+
+
+@dataclass
+class _FakeTxn:
+    request: Any
+    done: simpy.Event
+    result_data: dict[str, Any] = field(default_factory=dict)
+
+
+def _make(env, strict: bool = True):
+    node = Node(
+        id="sip0.cube0.pe0.pe_ipcq", kind="pe_ipcq",
+        impl="builtin.pe_ipcq",
+        attrs={"strict_validation": strict},
+        pos_mm=None,
+    )
+    comp = PeIpcqComponent(node, ctx=None)
+    comp.in_ports["host"] = simpy.Store(env)
+    comp.out_ports["sip0.cube0.pe0.pe_dma"] = simpy.Store(env)
+    comp.start(env)
+
+    peer_credit = simpy.Store(env)
+    ep = IpcqEndpoint(
+        sip=0, cube=0, pe=1, buffer_kind="tcm",
+        rx_base_pa=0x10_000, rx_base_va=0,
+        n_slots=4, slot_size=4096,
+    )
+    init_msg = IpcqInitMsg(
+        correlation_id="t", request_id="t",
+        target_sips=(0,), target_cubes=(0,), target_pe=0,
+        entries=(IpcqInitEntry(
+            direction="W", peer=ep,
+            my_rx_base_pa=0x40_000, my_rx_base_va=0,
+            n_slots=4, slot_size=4096,
+            peer_credit_store=peer_credit,
+        ),),
+        backpressure_mode="sleep",
+        buffer_kind="tcm",
+        credit_size_bytes=16,
+    )
+    done = env.event()
+    comp.in_ports["host"].put(_FakeTxn(request=init_msg, done=done))
+    env.run(until=done)
+    return comp
+
+
+# ── F2 tests ─────────────────────────────────────────────────────────
+
+
+def test_strict_mode_dtype_mismatch_raises():
+    env = simpy.Environment()
+    comp = _make(env, strict=True)
+
+    # Pre-arrive metadata with f32 dtype
+    fake_token = IpcqDmaToken(
+        src_addr=0, src_space="tcm",
+        dst_addr=0x40_000, dst_endpoint=comp._queue_pairs["W"]["peer"],
+        nbytes=64, handle_id="x",
+        shape=(8,), dtype="f32",  # mismatched
+        sender_seq=0,
+        src_sip=0, src_cube=0, src_pe=1, src_direction="E",
+    )
+    comp.in_ports["host"].put(IpcqMetaArrival(token=fake_token))
+    env.run(until=5)
+
+    # recv expecting f16 → should raise on strict
+    recv_cmd = IpcqRecvCmd(direction="W", shape=(8,), dtype="f16", handle_id="r")
+    req = IpcqRequest(command=recv_cmd, done=env.event())
+    comp.in_ports["host"].put(req)
+    with pytest.raises(ValueError, match="dtype"):
+        env.run(until=req.done)
+
+
+def test_strict_mode_shape_mismatch_raises():
+    env = simpy.Environment()
+    comp = _make(env, strict=True)
+
+    fake_token = IpcqDmaToken(
+        src_addr=0, src_space="tcm",
+        dst_addr=0x40_000, dst_endpoint=comp._queue_pairs["W"]["peer"],
+        nbytes=64, handle_id="x",
+        shape=(16,), dtype="f16",  # wrong shape
+        sender_seq=0,
+        src_sip=0, src_cube=0, src_pe=1, src_direction="E",
+    )
+    comp.in_ports["host"].put(IpcqMetaArrival(token=fake_token))
+    env.run(until=5)
+
+    recv_cmd = IpcqRecvCmd(direction="W", shape=(8,), dtype="f16", handle_id="r")
+    req = IpcqRequest(command=recv_cmd, done=env.event())
+    comp.in_ports["host"].put(req)
+    with pytest.raises(ValueError, match="shape"):
+        env.run(until=req.done)
+
+
+def test_non_strict_mode_silently_accepts():
+    env = simpy.Environment()
+    comp = _make(env, strict=False)
+
+    fake_token = IpcqDmaToken(
+        src_addr=0, src_space="tcm",
+        dst_addr=0x40_000, dst_endpoint=comp._queue_pairs["W"]["peer"],
+        nbytes=64, handle_id="x",
+        shape=(16,), dtype="f32",  # both wrong
+        sender_seq=0,
+        src_sip=0, src_cube=0, src_pe=1, src_direction="E",
+    )
+    comp.in_ports["host"].put(IpcqMetaArrival(token=fake_token))
+    env.run(until=5)
+
+    recv_cmd = IpcqRecvCmd(direction="W", shape=(8,), dtype="f16", handle_id="r")
+    req = IpcqRequest(command=recv_cmd, done=env.event())
+    comp.in_ports["host"].put(req)
+    env.run(until=req.done)
+    assert req.done.triggered  # no exception