Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)

Major changes:

PE-level IPCQ infrastructure:
- New PE_IPCQ component: ring-buffer control plane with 4-direction
  neighbor mapping, head/tail pointers, backpressure (poll/sleep).
- PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA,
  including in-flight data snapshot (D9) and op_log recording at
  outbound time for Phase 2 replay correctness.
- IpcqDmaToken piggyback model: data + metadata travel together,
  atomic visibility at receiver (invariant I6).
- Credit return fast path: bottleneck-BW latency, no fabric vc_comm.

Phase 2 data execution (ADR-0020 integration):
- op_log extended: DmaWriteCmd now captures src_space/src_addr for
  Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time.
- DataExecutor replays dma_write + ipcq_copy in t_start order.
- Engine._flush_data_phase: incremental cursor-based replay after
  each engine.wait() so host reads see post-Phase-2 data.
- KernelRunner Phase 1 writes disabled when op_log is active to
  prevent stale data from corrupting the MemoryStore snapshot.

TLContext / kernel API:
- tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype),
  tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode.
- TensorHandle operator overloading (add/sub/mul/div) via thread-local
  active TLContext → MathCmd dispatch through PE_MATH.
- PE-local scratch allocator for math output handles.
- tl.load returns space="hbm" handles for correct Phase 2 addressing.
- Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv.

Unified ccl_allreduce bench (PyTorch-compat host code):
- Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch)
  split matching real PyTorch DDP worker pattern.
- torch.distributed facade: init_process_group, get_world_size,
  get_rank, get_backend, all_reduce, barrier — only real PyTorch names.
- AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches
  kernel via tensor shard metadata (n_elem from shards[0].nbytes).
- world_size derived from topology spec (sips × cubes × pes_per_cube)
  with optional algorithm-level override in ccl.yaml.

Tensor API (PyTorch-compat surface):
- Tensor.numpy(): gather-aware (all shards via VA-based addressing).
- Tensor.copy_(source): scatter from host tensor into sharded target.
- RuntimeContext.from_numpy(arr): host-side staging tensor.
- Tensor.data property fixed to use numpy() (was shards[0]-only).

Algorithm modules moved to src/kernbench/ccl/algorithms/:
- ring_allreduce, mesh_allreduce, tree_allreduce, hello_send.
- Each module exports kernel_args(world_size, n_elem) helper.
- ccl.yaml module paths updated to kernbench.ccl.algorithms.*.

Dead code removed:
- 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.).
- _run_ccl_bench greenlet-per-SIP scheduler.
- benches.loader.is_ccl_bench + run_rank detection.
- benches/ccl/ directory.

Tests:
- New test_ccl_allreduce_matrix.py: 7 parametrized cases
  (ring×3 buffers, ring 8/16, mesh 4, tree 7).
- New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests.
- Existing tests updated for new import paths + world_size_override.

Docs:
- Korean ccl-author-guide.md and ADR-0023 paths updated.
- New English versions: ccl-author-guide.en.md, ADR-0023.en.md.

502 tests pass.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

tests/test_cross_sip_routing.py

@@ -0,0 +1,73 @@
+"""Cross-SIP PE_DMA routing tests (ADR-0023, topology v2).
+
+Verifies that PE_DMA in one SIP can route to PE_DMA in another SIP via
+the bidirectional pcie_ep ↔ fabric.switch0 path. Required for IPCQ
+multi-SIP collectives.
+"""
+from __future__ import annotations
+
+import pytest
+
+from kernbench.policy.routing.router import PathRouter, RoutingError
+from kernbench.topology.builder import resolve_topology
+
+
+def _topo():
+    return resolve_topology("topology.yaml").topology_obj
+
+
+# ── New edge ────────────────────────────────────────────────────────
+
+
+def test_pcie_ep_to_switch_edge_exists():
+    """The reverse pcie_ep → switch edge must exist for outbound traffic."""
+    topo = _topo()
+    pairs = {(e.src, e.dst) for e in topo.edges}
+    assert ("sip0.io0.pcie_ep", "fabric.switch0") in pairs
+    assert ("sip1.io0.pcie_ep", "fabric.switch0") in pairs
+
+
+def test_existing_switch_to_pcie_ep_still_present():
+    """Host→device path must remain intact (regression)."""
+    topo = _topo()
+    pairs = {(e.src, e.dst) for e in topo.edges}
+    assert ("fabric.switch0", "sip0.io0.pcie_ep") in pairs
+    assert ("fabric.switch0", "sip1.io0.pcie_ep") in pairs
+
+
+# ── Cross-SIP path ──────────────────────────────────────────────────
+
+
+def test_router_finds_cross_sip_pe_dma_path():
+    topo = _topo()
+    r = PathRouter(topo)
+    path = r.find_path("sip0.cube0.pe0", "sip1.cube0.pe0.pe_dma")
+    assert len(path) > 0
+    assert path[0] == "sip0.cube0.pe0.pe_dma"
+    assert path[-1] == "sip1.cube0.pe0.pe_dma"
+    assert "fabric.switch0" in path
+
+
+def test_router_finds_cross_sip_far_pe_path():
+    """Last cube of sip0 → first cube of sip1."""
+    topo = _topo()
+    r = PathRouter(topo)
+    path = r.find_path("sip0.cube15.pe7", "sip1.cube0.pe0.pe_dma")
+    assert "fabric.switch0" in path
+
+
+# ── Regression: intra-SIP routing unchanged ─────────────────────────
+
+
+def test_router_intra_sip_path_unchanged():
+    topo = _topo()
+    r = PathRouter(topo)
+    path = r.find_path("sip0.cube0.pe0", "sip0.cube0.pe1.pe_dma")
+    assert "fabric.switch0" not in path  # should not detour through switch
+
+
+def test_router_intra_cube_path_unchanged():
+    topo = _topo()
+    r = PathRouter(topo)
+    path = r.find_path("sip0.cube0.pe0", "sip0.cube0.hbm_ctrl")
+    assert "fabric.switch0" not in path