Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)

Major changes:

PE-level IPCQ infrastructure:
- New PE_IPCQ component: ring-buffer control plane with 4-direction
  neighbor mapping, head/tail pointers, backpressure (poll/sleep).
- PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA,
  including in-flight data snapshot (D9) and op_log recording at
  outbound time for Phase 2 replay correctness.
- IpcqDmaToken piggyback model: data + metadata travel together,
  atomic visibility at receiver (invariant I6).
- Credit return fast path: bottleneck-BW latency, no fabric vc_comm.

Phase 2 data execution (ADR-0020 integration):
- op_log extended: DmaWriteCmd now captures src_space/src_addr for
  Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time.
- DataExecutor replays dma_write + ipcq_copy in t_start order.
- Engine._flush_data_phase: incremental cursor-based replay after
  each engine.wait() so host reads see post-Phase-2 data.
- KernelRunner Phase 1 writes disabled when op_log is active to
  prevent stale data from corrupting the MemoryStore snapshot.

TLContext / kernel API:
- tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype),
  tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode.
- TensorHandle operator overloading (add/sub/mul/div) via thread-local
  active TLContext → MathCmd dispatch through PE_MATH.
- PE-local scratch allocator for math output handles.
- tl.load returns space="hbm" handles for correct Phase 2 addressing.
- Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv.

Unified ccl_allreduce bench (PyTorch-compat host code):
- Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch)
  split matching real PyTorch DDP worker pattern.
- torch.distributed facade: init_process_group, get_world_size,
  get_rank, get_backend, all_reduce, barrier — only real PyTorch names.
- AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches
  kernel via tensor shard metadata (n_elem from shards[0].nbytes).
- world_size derived from topology spec (sips × cubes × pes_per_cube)
  with optional algorithm-level override in ccl.yaml.

Tensor API (PyTorch-compat surface):
- Tensor.numpy(): gather-aware (all shards via VA-based addressing).
- Tensor.copy_(source): scatter from host tensor into sharded target.
- RuntimeContext.from_numpy(arr): host-side staging tensor.
- Tensor.data property fixed to use numpy() (was shards[0]-only).

Algorithm modules moved to src/kernbench/ccl/algorithms/:
- ring_allreduce, mesh_allreduce, tree_allreduce, hello_send.
- Each module exports kernel_args(world_size, n_elem) helper.
- ccl.yaml module paths updated to kernbench.ccl.algorithms.*.

Dead code removed:
- 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.).
- _run_ccl_bench greenlet-per-SIP scheduler.
- benches.loader.is_ccl_bench + run_rank detection.
- benches/ccl/ directory.

Tests:
- New test_ccl_allreduce_matrix.py: 7 parametrized cases
  (ring×3 buffers, ring 8/16, mesh 4, tree 7).
- New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests.
- Existing tests updated for new import paths + world_size_override.

Docs:
- Korean ccl-author-guide.md and ADR-0023 paths updated.
- New English versions: ccl-author-guide.en.md, ADR-0023.en.md.

502 tests pass.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

tests/test_tl_ipcq_api.py

@@ -0,0 +1,95 @@
+"""Tests for tl.send / tl.recv API (ADR-0023 D4 + D9.5)."""
+from __future__ import annotations
+
+from typing import Any
+
+import simpy
+from greenlet import greenlet
+
+from kernbench.common.ipcq_types import (
+    IpcqRecvCmd,
+    IpcqRequest,
+    IpcqSendCmd,
+)
+from kernbench.triton_emu.tl_context import TLContext
+
+
+# ── Command-list mode (no runner) ────────────────────────────────────
+
+
+def test_tl_send_command_list_mode():
+    tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0)
+    tl.send(dir="E", src_addr=0x500, nbytes=64, shape=(8,), dtype="f16")
+    cmds = tl.commands
+    sends = [c for c in cmds if isinstance(c, IpcqSendCmd)]
+    assert len(sends) == 1
+    assert sends[0].direction == "E"
+    assert sends[0].src_addr == 0x500
+    assert sends[0].nbytes == 64
+
+
+def test_tl_recv_command_list_mode():
+    tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0)
+    handle = tl.recv(dir="W", shape=(8,), dtype="f16")
+    cmds = tl.commands
+    recvs = [c for c in cmds if isinstance(c, IpcqRecvCmd)]
+    assert len(recvs) == 1
+    assert recvs[0].direction == "W"
+    # In command-list mode (no runner), tl.recv returns a placeholder
+    # TensorHandle (no actual data movement happens until SimPy)
+    assert handle.shape == (8,)
+    assert handle.dtype == "f16"
+
+
+def test_tl_recv_round_robin_no_dir():
+    tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0)
+    tl.recv(shape=(8,), dtype="f16")
+    cmds = tl.commands
+    recvs = [c for c in cmds if isinstance(c, IpcqRecvCmd)]
+    assert recvs[0].direction is None
+
+
+# ── Runner mode (greenlet) ──────────────────────────────────────────
+
+
+class _StubRunner:
+    """Minimal runner that auto-responds to IpcqSendCmd / IpcqRecvCmd."""
+
+    def __init__(self) -> None:
+        self.received: list[Any] = []
+
+    def switch_to_simpy(self, cmd: Any) -> Any:
+        self.received.append(cmd)
+        if isinstance(cmd, IpcqSendCmd):
+            return None
+        if isinstance(cmd, IpcqRecvCmd):
+            # Return a fake slot dict
+            return {
+                "data": None,
+                "src_space": "tcm",
+                "src_addr": 0xABCD,
+                "direction": cmd.direction or "E",
+                "dtype": cmd.dtype,
+                "shape": cmd.shape,
+                "nbytes": 16,
+            }
+        return None
+
+
+def test_tl_send_runner_mode():
+    runner = _StubRunner()
+    tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0, runner=runner)
+    tl.send(dir="E", src_addr=0x500, nbytes=64, shape=(8,), dtype="f16")
+    assert len(runner.received) == 1
+    assert isinstance(runner.received[0], IpcqSendCmd)
+
+
+def test_tl_recv_runner_mode_returns_handle_with_slot_addr():
+    runner = _StubRunner()
+    tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0, runner=runner)
+    h = tl.recv(dir="W", shape=(8,), dtype="f16")
+    assert isinstance(runner.received[0], IpcqRecvCmd)
+    # The returned TensorHandle's addr should reflect the slot
+    assert h.addr == 0xABCD
+    assert h.shape == (8,)
+    assert h.dtype == "f16"