ADR-0023 D9.7+: charge PE↔bank fabric hop for SRAM/HBM IPCQ slots
Cube SRAM and HBM live on the cube NoC behind router-attached links (sram_to_router_bw_gbs=128, hbm_to_router_bw_gbs=256). Previously the slot-IO model treated them as if they were per-PE local, so the buffer_kind sweep showed TCM ≈ SRAM at 64 KB / PE. pe_ipcq._handle_recv and pe_dma._handle_ipcq_inbound now charge a PE→bank compute_drain_ns on top of the intrinsic slot-IO for SRAM/HBM. TCM stays free of this hop. Adds an internal IpcqRecvCmd.consume field that gates the recv-side hop+slot-IO charges (used by a follow-up diagnostic API; default True keeps current behavior). Post-fix at 64 KB / PE: TCM 12.0 µs < HBM 21.4 µs < SRAM 24.3 µs. SRAM is slowest because its 128 GB/s bank link is the narrowest in the system — narrower than HBM's 256 GB/s. The existing ordering test is rewritten from tcm<sram<hbm to tcm<hbm<sram and a new test_ipcq_buffer_kind_locations adds 3 invariants on the gap. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
This commit is contained in:
@@ -1,12 +1,12 @@
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buffer_kind,sip_topology,n_sips,n_elem,bytes_per_pe,latency_ns
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hbm,torus_2d,6,128,256,2002.0399999999827
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hbm,torus_2d,6,1024,2048,3541.0399999999827
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hbm,torus_2d,6,8192,16384,15889.03999999999
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hbm,torus_2d,6,32768,65536,58225.03999999998
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sram,torus_2d,6,128,256,1762.0399999999827
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sram,torus_2d,6,1024,2048,2293.0399999999827
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sram,torus_2d,6,8192,16384,6577.039999999986
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sram,torus_2d,6,32768,65536,21265.03999999992
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hbm,torus_2d,6,128,256,1858.0399999999827
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hbm,torus_2d,6,1024,2048,2389.0399999999827
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hbm,torus_2d,6,8192,16384,6673.039999999986
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hbm,torus_2d,6,32768,65536,21361.03999999992
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sram,torus_2d,6,128,256,1774.0399999999827
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sram,torus_2d,6,1024,2048,2389.0399999999827
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sram,torus_2d,6,8192,16384,7345.039999999986
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sram,torus_2d,6,32768,65536,24337.039999999935
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tcm,torus_2d,6,128,256,1678.0399999999827
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tcm,torus_2d,6,1024,2048,1957.0399999999827
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tcm,torus_2d,6,8192,16384,4225.039999999986
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Before Width: | Height: | Size: 68 KiB After Width: | Height: | Size: 74 KiB |
@@ -135,6 +135,13 @@ class IpcqRecvCmd:
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"return_slot" — return slot address as-is (default, zero-copy).
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Kernel uses the slot memory directly.
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"copy_to_dst" — copy slot data to dst_addr, then return.
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``consume`` (DIAGNOSTIC ONLY): when False, recv still blocks until the
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payload lands in the slot, but skips the slot-read latency charge
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(slot-IO + PE↔bank fabric drain for SRAM/HBM tiers). This exists
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solely so the pe2pe overview plot can compare apples-to-apples
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against tl.store (a one-sided write that pays no read on DST). Real
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kernels always need the data they receive — leave this True.
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"""
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direction: str | None # None → round-robin (weak fairness, D4)
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@@ -146,6 +153,7 @@ class IpcqRecvCmd:
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dst_space: str = "" # used only when recv_mode == "copy_to_dst"
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blocking: bool = True
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data_op: bool = True
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consume: bool = True # DIAGNOSTIC: see docstring
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# ── D12: IpcqDmaToken (PE_IPCQ → PE_DMA, vc_comm) ───────────────────
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@@ -222,10 +222,24 @@ class PeDmaComponent(PeEngineBase):
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# ADR-0023 D9.7: charge IPCQ slot-WRITE latency against the
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# backing-memory tier (tcm/sram/hbm) before the atomic block.
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# Must come BEFORE the atomic write→IpcqMetaArrival pair (I6).
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# SRAM/HBM also pay a PE_DMA→bank fabric drain (slot lives on
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# the cube NoC); TCM is per-PE local and skips this hop.
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from kernbench.common.ipcq_types import slot_io_latency_ns
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slot_write_ns = slot_io_latency_ns(
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token.dst_endpoint.buffer_kind, token.nbytes,
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)
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buffer_kind = token.dst_endpoint.buffer_kind
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if buffer_kind in ("sram", "hbm") and self.ctx is not None:
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cube_prefix = self._pe_prefix.rsplit(".", 1)[0]
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bank_node = (
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f"{cube_prefix}.sram" if buffer_kind == "sram"
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else f"{cube_prefix}.hbm_ctrl"
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)
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try:
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path = self.ctx.router.find_path(self._pe_prefix, bank_node)
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bank_drain_ns = self.ctx.compute_drain_ns(path, token.nbytes)
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if bank_drain_ns > 0:
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yield env.timeout(bank_drain_ns)
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except Exception:
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pass
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slot_write_ns = slot_io_latency_ns(buffer_kind, token.nbytes)
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if slot_write_ns > 0:
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yield env.timeout(slot_write_ns)
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@@ -332,12 +332,37 @@ class PeIpcqComponent(ComponentBase):
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# ADR-0023 D9.7: charge IPCQ slot-READ latency against the
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# backing-memory tier (tcm/sram/hbm). Recv blocks for the
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# kernel-side slot consume; pe_exec_ns reflects this cost.
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# SRAM/HBM live on the cube NoC behind a router-attached link,
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# so reading a slot also pays a PE→bank fabric drain. TCM is
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# per-PE local and skips this hop.
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#
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# cmd.consume is a DIAGNOSTIC flag (default True). When False,
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# the read charges below are skipped — used only by the pe2pe
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# overview plot for an apples-to-apples comparison against
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# tl.store (one-sided write, no read on DST). Real kernels
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# always consume; this branch must not be exercised in
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# production code paths.
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from kernbench.common.ipcq_types import slot_io_latency_ns
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slot_read_ns = slot_io_latency_ns(
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self._buffer_kind, req.result_data.get("nbytes", 0),
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)
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if slot_read_ns > 0:
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yield env.timeout(slot_read_ns)
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nbytes = req.result_data.get("nbytes", 0)
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if cmd.consume:
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if self._buffer_kind in ("sram", "hbm") and self.ctx is not None:
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cube_prefix = self._pe_prefix.rsplit(".", 1)[0]
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bank_node = (
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f"{cube_prefix}.sram" if self._buffer_kind == "sram"
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else f"{cube_prefix}.hbm_ctrl"
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)
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try:
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path = self.ctx.router.find_path(
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self._pe_prefix, bank_node,
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)
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bank_drain_ns = self.ctx.compute_drain_ns(path, nbytes)
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if bank_drain_ns > 0:
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yield env.timeout(bank_drain_ns)
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except Exception:
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pass
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slot_read_ns = slot_io_latency_ns(self._buffer_kind, nbytes)
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if slot_read_ns > 0:
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yield env.timeout(slot_read_ns)
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# Diagnostics trace (D14)
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from kernbench.ccl import diagnostics
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@@ -43,20 +43,30 @@ from tests.test_allreduce_multidevice import (
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)
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# Expected per-tier BW + overhead (Phase 2 will encode this in
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# pe_ipcq.py). Mirrors topology.yaml component values.
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_EXPECTED_BW = {
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"tcm": (512.0, 0.0),
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"sram": (512.0, 2.0),
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"hbm": (256.0, 6.0),
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# Expected per-tier (slot intrinsic BW, fixed overhead, PE↔bank hop BW).
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# Slot intrinsic mirrors _BUFFER_KIND_BW in src/kernbench/common/ipcq_types.py.
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# PE↔bank hop reflects topology.yaml link BWs:
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# - TCM is per-PE local → no hop, encoded as inf.
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# - SRAM bank sits on cube NoC behind sram_to_router_bw_gbs = 128 GB/s.
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# - HBM ctrl sits on cube NoC behind hbm_to_router_bw_gbs = 256 GB/s.
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_EXPECTED_TIER = {
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"tcm": {"slot_bw_gbs": 512.0, "overhead_ns": 0.0, "bank_hop_bw_gbs": float("inf")},
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"sram": {"slot_bw_gbs": 512.0, "overhead_ns": 2.0, "bank_hop_bw_gbs": 128.0},
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"hbm": {"slot_bw_gbs": 256.0, "overhead_ns": 6.0, "bank_hop_bw_gbs": 256.0},
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}
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def _expected_slot_io_ns(buffer_kind: str, nbytes: int) -> float:
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"""Per-access latency the model is expected to add (write OR read)."""
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bw_gbs, overhead_ns = _EXPECTED_BW[buffer_kind]
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# 1 GB/s = 1 byte/ns
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return nbytes / bw_gbs + overhead_ns
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"""Per-access latency the model is expected to add (write OR read).
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Includes the PE↔bank fabric hop for non-TCM tiers — SRAM and HBM
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live on the cube NoC behind a router-attached link, so each slot
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access pays a fabric drain in addition to the intrinsic slot-IO.
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"""
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tier = _EXPECTED_TIER[buffer_kind]
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bank_hop_ns = nbytes / tier["bank_hop_bw_gbs"]
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slot_io_ns = nbytes / tier["slot_bw_gbs"] + tier["overhead_ns"]
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return bank_hop_ns + slot_io_ns
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def _run_torus_allreduce(
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@@ -114,12 +124,19 @@ def _run_torus_allreduce(
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# ── Phase 1 assertions ───────────────────────────────────────────────
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def test_slot_write_latency_orders_tcm_sram_hbm(tmp_path):
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"""tcm < sram < hbm at 8192 B per send.
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def test_slot_write_latency_orders_tcm_hbm_sram(tmp_path):
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"""tcm < hbm < sram at 8192 B per send.
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Pre-Phase-2: all three return the same pe_exec_ns and this
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assertion fails. Post-Phase-2: the per-tier BW + overhead make
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hbm visibly slower than sram, which is slower than tcm.
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The ordering is set by the topology link BWs, NOT the intrinsic slot
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cell rates: SRAM and HBM both live on the cube NoC behind a router
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link, and SRAM's link (128 GB/s) is the narrowest in the system —
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narrower than HBM's (256 GB/s). So once the PE↔bank hop is charged,
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SRAM ends up the slowest tier even though its slot cell array has
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the same intrinsic BW as TCM.
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Pre-fix model misses the PE↔bank hop entirely → assertion FAILS
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(today's ordering is tcm < sram < hbm). Post-fix model includes the
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hop → assertion PASSES.
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"""
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n_elem = 4096 # 8192 B per slot
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lat_tcm = _run_torus_allreduce(tmp_path, buffer_kind="tcm", n_elem=n_elem)
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@@ -130,21 +147,22 @@ def test_slot_write_latency_orders_tcm_sram_hbm(tmp_path):
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exp_tcm = 2 * _expected_slot_io_ns("tcm", n_elem * 2)
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exp_sram = 2 * _expected_slot_io_ns("sram", n_elem * 2)
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exp_hbm = 2 * _expected_slot_io_ns("hbm", n_elem * 2)
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# Floor margin: 50% of the raw expected per-access delta — lets Phase 2
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# implementation choose to charge only one side without breaking the test,
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# but still requires a clearly observable gap.
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margin_sram_tcm = 0.5 * (exp_sram - exp_tcm)
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margin_hbm_sram = 0.5 * (exp_hbm - exp_sram)
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# Floor margin: 50% of the raw expected per-access delta — lets the
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# implementation choose to charge only one side without breaking the
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# test, but still requires a clearly observable gap.
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margin_hbm_tcm = 0.5 * (exp_hbm - exp_tcm)
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margin_sram_hbm = 0.5 * (exp_sram - exp_hbm)
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assert lat_sram > lat_tcm + margin_sram_tcm, (
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f"sram should be slower than tcm by ≥ {margin_sram_tcm:.1f} ns "
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f"per allreduce, got sram={lat_sram:.1f} tcm={lat_tcm:.1f} "
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f"(delta={lat_sram - lat_tcm:.1f})"
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assert lat_hbm > lat_tcm + margin_hbm_tcm, (
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f"hbm should be slower than tcm by ≥ {margin_hbm_tcm:.1f} ns "
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f"per allreduce, got hbm={lat_hbm:.1f} tcm={lat_tcm:.1f} "
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f"(delta={lat_hbm - lat_tcm:.1f})"
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)
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assert lat_hbm > lat_sram + margin_hbm_sram, (
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f"hbm should be slower than sram by ≥ {margin_hbm_sram:.1f} ns "
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f"per allreduce, got hbm={lat_hbm:.1f} sram={lat_sram:.1f} "
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f"(delta={lat_hbm - lat_sram:.1f})"
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assert lat_sram > lat_hbm + margin_sram_hbm, (
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f"sram should be slower than hbm by ≥ {margin_sram_hbm:.1f} ns "
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f"per allreduce (sram bank link 128 GB/s is narrower than hbm "
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f"link 256 GB/s), got sram={lat_sram:.1f} hbm={lat_hbm:.1f} "
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f"(delta={lat_sram - lat_hbm:.1f})"
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)
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@@ -0,0 +1,208 @@
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"""Phase 1 micro-tests for IPCQ slot-memory PHYSICAL placement.
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The current model in ``_BUFFER_KIND_BW`` (src/kernbench/common/ipcq_types.py)
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charges only an intrinsic-memory term for IPCQ slot read/write::
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TCM: nbytes/512 + 0
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SRAM: nbytes/512 + 2
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HBM: nbytes/256 + 6
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This treats SRAM and HBM as if they were per-PE local. The topology
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declares the opposite — both live on the cube NoC, behind their own
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router-attached link::
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topology.yaml:130 sram_to_router_bw_gbs: 128.0
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topology.yaml:129 hbm_to_router_bw_gbs: 256.0
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So a correct model must charge a PE→bank fabric drain for SRAM and HBM
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on both ``tl.send`` (writer landing bytes into the cube SRAM/HBM bank
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via PE_DMA → router → bank) and ``tl.recv`` (reader pulling bytes back
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across the same link). TCM stays free of that hop because it is
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genuinely per-PE local.
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The three tests below run the existing torus_2d 6-SIP allreduce harness
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with ``buffer_kind`` flipped between tcm/sram/hbm and assert invariants
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that the post-fix model must satisfy. They EXPECT TO FAIL today because
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the simulator under-charges SRAM and HBM by skipping the PE↔bank hop.
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Phase 2 will edit:
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- src/kernbench/components/builtin/pe_ipcq.py (_handle_recv: add
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compute_drain_ns(pe→bank, nbytes) for sram/hbm)
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- src/kernbench/components/builtin/pe_dma.py (_handle_ipcq_inbound:
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add second-leg drain for sram/hbm-destined slots)
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Tests must NEVER be weakened to make Phase 2 pass — invariants below
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follow from physics (link BW × payload), so any model reflecting the
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topology will satisfy them by construction.
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"""
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from __future__ import annotations
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from pathlib import Path
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import pytest
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import yaml
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from kernbench.runtime_api.context import RuntimeContext
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from kernbench.runtime_api.types import DeviceSelector
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from kernbench.sim_engine.engine import GraphEngine
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from kernbench.topology.builder import resolve_topology
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from tests.test_allreduce_multidevice import (
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_write_temp_configs,
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run_allreduce,
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)
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def _run_allreduce_with_buffer_kind(
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tmp_path: Path, *, buffer_kind: str, n_elem: int,
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) -> float:
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"""Run one torus_2d 6-SIP allreduce with the given buffer_kind and
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return critical-path pe_exec_ns (max across all PEs).
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Mirrors the sweep harness in test_allreduce_buffer_kind_sweep.py
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so the assertions below compare apples-to-apples against that PNG.
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"""
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sub = tmp_path / f"{buffer_kind}_{n_elem}"
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sub.mkdir()
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topo_path, ccl_path = _write_temp_configs(
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sub,
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sip_topology="torus_2d",
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n_sips=6,
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algorithm="intercube_allreduce",
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sip_w=3, sip_h=2,
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n_elem_override=n_elem,
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)
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with open(ccl_path) as f:
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ccl_cfg = yaml.safe_load(f)
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ccl_cfg.setdefault("defaults", {})["buffer_kind"] = buffer_kind
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ccl_cfg.setdefault("algorithms", {}).setdefault(
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"intercube_allreduce", {},
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)["buffer_kind"] = buffer_kind
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with open(ccl_path, "w") as f:
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yaml.dump(ccl_cfg, f, default_flow_style=False)
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topo = resolve_topology(topo_path)
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engine = GraphEngine(topo.topology_obj, enable_data=True)
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spec = topo.topology_obj.spec
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with RuntimeContext(
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engine=engine,
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target_device=DeviceSelector("all"),
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correlation_id=f"loc_{buffer_kind}_{n_elem}",
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spec=spec,
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) as ctx:
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result = run_allreduce(
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ctx, engine, spec,
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algorithm="intercube_allreduce", ccl_yaml=ccl_path,
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)
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assert result["ok_cubes"] > 0, "allreduce did not validate"
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pe_exec_vals = [
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float(tr.get("pe_exec_ns", 0.0) or 0.0)
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for _, (_, tr) in engine._results.items()
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if isinstance(tr, dict)
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]
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return max(pe_exec_vals) if pe_exec_vals else 0.0
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# ── Phase 1 assertions ───────────────────────────────────────────────
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||||
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def test_sram_meaningfully_slower_than_tcm_at_large_payload(tmp_path):
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"""At 32 KB / PE the SRAM-backed allreduce must take meaningfully
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||||
longer than the TCM-backed one because every IPCQ slot access goes
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through the 128 GB/s SRAM↔router link, while TCM stays per-PE local.
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|
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Floor justification (physics, not implementation):
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Per-IPCQ-roundtrip the SRAM tier adds 2 × nbytes/128 ns over TCM
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(one PE→SRAM hop on send-inbound, one SRAM→PE hop on recv).
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At 32 KB: 2 × 32768/128 = 512 ns added per slot exchange.
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With ≥ 10 critical-path exchanges in a 6-SIP torus_2d allreduce
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this is ≥ 5_120 ns. The threshold below is half that to leave
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||||
room for differing critical-path counting.
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||||
|
||||
Pre-Phase-2: gap is constant 48 ns (just the SRAM overhead × 24
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||||
slot accesses); test FAILS.
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Post-Phase-2: gap scales with payload; test PASSES.
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||||
"""
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||||
n_elem = 16384 # 32 KB / PE
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lat_tcm = _run_allreduce_with_buffer_kind(
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||||
tmp_path, buffer_kind="tcm", n_elem=n_elem,
|
||||
)
|
||||
lat_sram = _run_allreduce_with_buffer_kind(
|
||||
tmp_path, buffer_kind="sram", n_elem=n_elem,
|
||||
)
|
||||
delta = lat_sram - lat_tcm
|
||||
THRESHOLD_NS = 2_500.0
|
||||
assert delta > THRESHOLD_NS, (
|
||||
f"SRAM should be ≥ {THRESHOLD_NS:.0f} ns slower than TCM at 32 KB "
|
||||
f"because each IPCQ access pays a 128 GB/s PE↔SRAM hop. "
|
||||
f"got tcm={lat_tcm:.1f} sram={lat_sram:.1f} delta={delta:.1f} ns"
|
||||
)
|
||||
|
||||
|
||||
def test_sram_tcm_gap_scales_with_payload(tmp_path):
|
||||
"""The SRAM-vs-TCM gap must grow roughly linearly with payload size.
|
||||
|
||||
Pre-Phase-2: the only difference between TCM and SRAM is the SRAM
|
||||
per-access ``overhead_ns = 2``, which does NOT scale with payload —
|
||||
so the gap is the same constant 48 ns at 8 KB and at 32 KB. Ratio = 1.
|
||||
|
||||
Post-Phase-2: the dominant term is 2 × nbytes/128 (PE↔SRAM hop on
|
||||
write+read) which IS linear in payload. Going 8 KB → 32 KB (4×)
|
||||
should produce a gap roughly 4× larger.
|
||||
|
||||
Threshold below is 3× to keep slack for fixed-overhead effects.
|
||||
"""
|
||||
lat_tcm_small = _run_allreduce_with_buffer_kind(
|
||||
tmp_path, buffer_kind="tcm", n_elem=4096, # 8 KB
|
||||
)
|
||||
lat_sram_small = _run_allreduce_with_buffer_kind(
|
||||
tmp_path, buffer_kind="sram", n_elem=4096,
|
||||
)
|
||||
lat_tcm_large = _run_allreduce_with_buffer_kind(
|
||||
tmp_path, buffer_kind="tcm", n_elem=16384, # 32 KB
|
||||
)
|
||||
lat_sram_large = _run_allreduce_with_buffer_kind(
|
||||
tmp_path, buffer_kind="sram", n_elem=16384,
|
||||
)
|
||||
|
||||
gap_small = lat_sram_small - lat_tcm_small
|
||||
gap_large = lat_sram_large - lat_tcm_large
|
||||
|
||||
assert gap_small > 0, (
|
||||
f"sanity: SRAM should never be FASTER than TCM, "
|
||||
f"got gap_small={gap_small:.1f} ns"
|
||||
)
|
||||
assert gap_large > 3.0 * gap_small, (
|
||||
f"4× payload should produce ≥3× SRAM/TCM gap (linear in nbytes "
|
||||
f"because of the 128 GB/s PE↔SRAM hop). "
|
||||
f"got gap_small={gap_small:.1f} (8KB), gap_large={gap_large:.1f} "
|
||||
f"(32KB), ratio={gap_large / max(gap_small, 1e-9):.2f}"
|
||||
)
|
||||
|
||||
|
||||
def test_hbm_pe_hop_charged_at_large_payload(tmp_path):
|
||||
"""At 32 KB / PE the HBM-vs-TCM gap must exceed the gap that comes
|
||||
purely from HBM's 256 GB/s intrinsic slot-IO disadvantage.
|
||||
|
||||
Pre-Phase-2 the entire HBM/TCM gap is just the slot-IO term
|
||||
(24 × (nbytes/512 + 6) ≈ 1_700 ns at 32 KB). Post-fix adds another
|
||||
24 × (nbytes/256) × 2 ≈ 6_144 ns from the PE↔HBM hop on send and
|
||||
recv, so the total HBM/TCM gap should clearly clear 4 µs.
|
||||
"""
|
||||
n_elem = 16384 # 32 KB / PE
|
||||
lat_tcm = _run_allreduce_with_buffer_kind(
|
||||
tmp_path, buffer_kind="tcm", n_elem=n_elem,
|
||||
)
|
||||
lat_hbm = _run_allreduce_with_buffer_kind(
|
||||
tmp_path, buffer_kind="hbm", n_elem=n_elem,
|
||||
)
|
||||
delta = lat_hbm - lat_tcm
|
||||
THRESHOLD_NS = 4_000.0
|
||||
assert delta > THRESHOLD_NS, (
|
||||
f"HBM should be ≥ {THRESHOLD_NS:.0f} ns slower than TCM at 32 KB "
|
||||
f"once the 256 GB/s PE↔HBM hop is charged on each IPCQ access. "
|
||||
f"got tcm={lat_tcm:.1f} hbm={lat_hbm:.1f} delta={delta:.1f} ns"
|
||||
)
|
||||
Reference in New Issue
Block a user