sim: pin compute outputs and on-chip recv slots for composite operands

src/kernbench/triton_emu/tl_context.py

@@ -697,6 +697,10 @@ class TLContext:
                 nbytes=self._nbytes(shape, dtype),
                 data=data,
                 space=slot_space,
+                # On-chip (tcm/sram) IPCQ slot: read in place as a composite
+                # operand, not DMA_READ of its non-HBM slot address. An HBM
+                # slot is a valid PA, so it stays unpinned (DMA streams it).
+                pinned=slot_space != "hbm",
             )
         return self._make_handle(addr=0, shape=shape, dtype=dtype)
 
@@ -738,6 +742,7 @@ class TLContext:
                 nbytes=self._nbytes(shape, dtype),
                 data=None,
                 space=slot_space,
+                pinned=slot_space != "hbm",
             )
         return self._make_handle(addr=0, shape=shape, dtype=dtype)
 
@@ -1105,6 +1110,7 @@ class TLContext:
                 nbytes=self._nbytes(handle.cmd.shape, handle.cmd.dtype),
                 data=data,
                 space=slot_space,
+                pinned=slot_space != "hbm",
             )
             handle.resolved = True
             handle.result = th