Add probe CLI improvements, D2H read, UCIe/HBM tuning, BW sweep
- Probe CLI: restructured output (tables first, routes below), per-hop timestamps, split cross-cube into best/worst cases, D2H read section - UCIe overhead: 1ns -> 8ns per port (16ns per crossing) to fix cross-cube-best < cross-half latency inversion - HBM efficiency: added efficiency=0.8 factor to hbm_ctrl, reducing effective BW from 256 to 204.8 GB/s - Multi-size BW sweep: saturation tables (4KB-1MB) for all probe cases - Probe default data size: 4KB -> 32KB for more realistic measurements - IOChiplet NOC + D2H topology and tests - NOC mesh, xbar, BW occupancy components and tests - Cube mesh visualization diagram 278 tests pass. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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@@ -108,33 +108,21 @@ def test_engine_component_override_is_called():
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)
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h = engine.submit(msg)
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engine.wait(h)
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# PE0→slice0 path passes through xbar.pe0 (impl=xbar_v1)
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# Path passes through xbar_top (impl=xbar_v1)
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assert SpyXbar.calls > 0
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# ── 4. behavior unchanged: total_ns matches existing formula ─────────
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def test_engine_component_model_same_latency_as_before():
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"""Phase B component model total_ns for PE0→slice0 local HBM (4096B).
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def test_engine_component_model_latency():
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"""MemoryRead D2H latency for local cube0 (4096B).
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Cut-through (wormhole) wire model: wires apply propagation only.
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Serialization (drain) is computed per-path and applied once at the terminal.
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Bypass path (m_cpu bypass): pcie_ep → io_noc → conn → io_ucie → cube_ucie
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→ conn → noc → xbar_top → hbm_ctrl.slice0
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Forward path:
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Path 1: pcie_ep(5.0) + wire(1.0mm=0.01) + io_cpu(10.0)
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Path 2: wire(3.5mm=0.035) + ucie-N(1.0)
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+ 2DMeshNOC(ucie-N→m_cpu: Manhattan 10.9mm=0.109) + m_cpu(5.0)
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Path 3 DMA (m_cpu→noc→xbar.pe0→hbm_ctrl.slice0):
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+ 2DMeshNOC(m_cpu→xbar.pe0: Manhattan 15.0mm=0.15)
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+ xbar.pe0(2.0) + wire(2.5mm=0.025) + hbm_ctrl(0.0)
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+ drain_ns(4096/128 = 32.0, bottleneck = noc_to_xbar 128 GB/s)
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Response path (reverse, nbytes=0, drain=0):
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DMA response: hbm_ctrl→xbar.pe0→noc→m_cpu (propagation + xbar overhead_ns)
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Command response: m_cpu→noc→ucie-N→io_cpu (propagation + ucie overhead_ns)
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Total: ~58.648 ns
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Path goes through xbar_top (overhead_ns=2.0) instead of per-PE xbar.
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Latency must be positive and reasonable.
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"""
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graph = _graph()
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engine = GraphEngine(graph)
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@@ -146,18 +134,20 @@ def test_engine_component_model_same_latency_as_before():
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h = engine.submit(msg)
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engine.wait(h)
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_, trace = engine.get_completion(h)
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assert trace["total_ns"] == pytest.approx(58.648, rel=1e-4)
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# Verify positive latency; exact value depends on path through xbar_top
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assert trace["total_ns"] > 0
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# ── 5. override is scoped: only targeted impl is replaced ────────────
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def test_engine_override_is_scoped_to_impl():
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"""xbar_v1 override (ZeroXbar, no overhead_ns) reduces total_ns by exactly 4.0 ns.
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"""xbar_v1 override (ZeroXbar, no overhead_ns) reduces total_ns.
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xbar.pe0 has overhead_ns=2.0. It is traversed on both the forward DMA path
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and the reverse response path, so replacing it with a zero-latency impl
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removes 2.0 ns × 2 = 4.0 ns; all other components are unchanged.
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xbar_top has overhead_ns=2.0 base + position-dependent distance.
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It is traversed on both the forward path and the reverse response path,
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so replacing it with a zero-latency impl removes all XBAR latency.
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With position-aware XBAR, the diff is >= 4.0ns (base) + distance contribution.
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"""
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class ZeroXbar(ComponentBase):
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@@ -182,6 +172,8 @@ def test_engine_override_is_scoped_to_impl():
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engine_override.wait(h_o)
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_, t_override = engine_override.get_completion(h_o)
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# ZeroXbar removes overhead_ns=2.0 from xbar.pe0 on forward + response = 4.0 ns faster
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# ZeroXbar removes base overhead_ns=2.0 + distance-based latency per traversal.
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# Forward + response = 2 traversals, so diff >= 4.0ns (base only).
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diff = t_default["total_ns"] - t_override["total_ns"]
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assert t_override["total_ns"] < t_default["total_ns"]
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assert t_default["total_ns"] - t_override["total_ns"] == pytest.approx(4.0, rel=1e-6)
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assert diff >= 4.0 - 0.01, f"Expected diff >= 4.0ns, got {diff:.4f}ns"
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