paper: add /paper skill + 1H HW-SW codesign report (GEMM, All-Reduce, fused GQA)
New `/paper` slash-command skill that synthesizes ADR/SPEC content and live KernBench benchmark results into a sectioned LaTeX technical paper compiled to PDF with Tectonic (auto-installed). The skill negotiates a TOC, grounds every number in committed artifacts or fresh bench runs, and keeps report-only benches isolated. This commit also includes the first generated report: - docs/report/1H-codesign-paper/ — main.tex + per-section .tex, figures, toc.md contract, and the built 8-page main.pdf. Covers the platform (source-level kernels, latency model + accuracy, HW config from topology.yaml), GEMM via composite command, All-Reduce via PE_IPCQ, and fused GQA combining both, plus discussion/conclusion/2H future work. - scripts/paper/ — isolated report harnesses (not registered benches): paper_gqa_latency.py harvests per-panel GQA end-to-end latency + engine occupancy (the milestone only emitted op-counts); paper_plot_gqa.py renders the GQA figures. GEMM/All-Reduce reuse committed milestone figures/CSVs; GQA results are generated fresh. Honest flags retained: PE_CPU dispatch cost is 0 in this config, and the proposed two-composite softmax_merge decode is marked designed-not-measured. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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\section*{Executive Summary}
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\addcontentsline{toc}{section}{Executive Summary}
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This report studies how to make attention-centric LLM kernels fast through
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hardware--software codesign, using KernBench, a discrete-event simulator
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that runs kernels at the source level---without a compiler or other
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software-stack dependency---so that algorithm-level optimizations and the
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hardware features that support them can be isolated and measured.
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The 1H work centers on attention. Building on prior multi-head-attention
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work, we target FlashAttention-style Grouped-Query Attention (GQA) and find
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that a fast fused attention kernel rests on two enabling optimizations,
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each studied in its own right and then combined inside the fused kernel:
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a \textbf{composite command} that issues a tiled GEMM as a single,
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self-routing pipeline, and \textbf{PE\_IPCQ}, a per-PE on-device collective
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engine for all-reduce.
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The measured results form a single, consistent story. For GEMM, the
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composite command lets compute-rich shapes reach
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\textasciitilde\SI{78}{\percent} of peak MAC efficiency, with the simulator's
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measured efficiency tracking the analytic prediction within
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\SIrange{10}{20}{\percent}---both a performance result and a validation of
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the latency model. For all-reduce, PE\_IPCQ delivers on-device collectives
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whose latency tracks the interconnect's physical limits; a 2D-torus
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inter-device fabric is \SI{20}{}--\SI{25}{\percent} faster than a mesh or
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ring at scale, and staging the collective in on-PE TCM rather than HBM or
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SRAM saves a further \SI{14}{}--\SI{38}{\percent}. For fused GQA, the two
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enablers combine: because the composite command keeps the MAC array nearly
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idle, the kernel is exposed as overwhelmingly data-movement bound---the DMA
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engine outweighs the compute engines by two to three orders of magnitude,
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and on-device IPCQ reduction traffic scales with users and devices.
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\textbf{Bottom line.} For an attention-dominated decoder, the hardware
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changes worth keeping are the ones that move and reduce data faster: the
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single-command self-routing GEMM pipeline (which makes the MAC array
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usable and exposes the real bottleneck), the on-device PE\_IPCQ collective
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with its compute/communication virtual-channel split, fast on-PE staging
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memory, and wrap-around (torus) inter-device links. Additional raw MAC
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throughput is not the limiting factor for this workload.
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\section{Introduction}
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\label{sec:intro}
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The performance of a large language model on an accelerator is decided less
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by peak FLOPS than by how well the kernel exploits the memory system and
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the interconnect. This is especially true of attention, which in the
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decode phase reads a large KV cache to do a small amount of arithmetic.
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Optimizing such kernels is fundamentally a \emph{codesign} problem: the
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algorithm (how to tile, fuse, and reduce) and the hardware (what issue
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mechanism, what collective engine, what memory hierarchy) have to be
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designed against each other. Optimizing only the software leaves the
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hardware idle; adding hardware that the software cannot reach is wasted
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area.
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\paragraph{The 1H focus: attention.} This half's work targets attention.
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Multi-head attention (MHA) was studied previously and is taken here as the
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established baseline. The new work is FlashAttention-style tiling and
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Grouped-Query Attention (GQA)---the form used by modern long-context
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decoders, in which several query heads share a single KV head to shrink the
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KV cache. Realizing a fast \emph{fused} GQA kernel, however, is not a
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single optimization. It decomposes into two enabling optimizations that we
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studied separately and then brought together inside the fused kernel:
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\begin{enumerate}
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\item \textbf{GEMM optimization} via a composite command
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(\S\ref{sec:gemm}): a way to issue a tiled matrix multiply as one
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self-routing pipeline so the MAC array stays fed without per-tile command
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overhead. Attention's $Q\!\cdot\!K^{\top}$ and $P\!\cdot\!V$ products are
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exactly such GEMMs.
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\item \textbf{Communication optimization} via PE\_IPCQ
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(\S\ref{sec:allreduce}): a per-PE on-device collective engine that
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performs all-reduce overlapped with compute. Attention's multi-user and
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sequence-parallel KV reductions are exactly such collectives.
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\end{enumerate}
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The report therefore reads as \emph{two enablers building to one capstone}:
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GEMM (\S\ref{sec:gemm}) and all-reduce (\S\ref{sec:allreduce}) are
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developed and measured on their own, and then fused GQA
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(\S\ref{sec:gqa}) shows them operating together. Before the results,
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\S\ref{sec:platform} describes the KernBench platform---why a
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software-stack-independent, source-level simulator is the right tool for
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this question, how it executes a kernel, how it computes latency and how
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accurate that is, and the exact hardware configuration used throughout.
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We close with a cross-cutting discussion of which hardware changes are
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worth their cost (\S\ref{sec:discussion}), a conclusion
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(\S\ref{sec:conclusion}), and the 2H agenda
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(\S\ref{sec:future}): extending from attention to the feed-forward and
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mixture-of-experts layers, and to the compute/data distribution questions
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that full LLM decoding and agentic workloads raise.
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\section{The KernBench Platform}
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\label{sec:platform}
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All results in this report are produced on \emph{KernBench}, a
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system-level, discrete-event simulator for LLM kernels running on
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SIP-based AI accelerators. This section explains why the platform exists,
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how it executes a kernel, how it computes latency and how accurate that
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number is, and the concrete hardware configuration used for every
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experiment that follows.
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\subsection{Why KernBench: source-level kernels without a software stack}
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\label{sec:why}
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In a production end-to-end (E2E) stack, kernel performance is entangled
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with every layer above the hardware: the compiler's tiling and
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scheduling choices, the framework's operator dispatch, the collective
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library, and the runtime. Good E2E numbers require \emph{all} of those
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layers to be co-optimized, which makes it hard to answer a narrower but
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more fundamental question: \emph{given the hardware, how fast can a
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well-written kernel be, and which hardware features actually make it
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faster?}
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KernBench is built to answer exactly that question. Kernels are written
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and executed at the \emph{source level}---as algorithmic descriptions in a
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small tile-oriented kernel API---with no dependency on a compiler or any
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other software-stack layer. The simulator takes the kernel and a hardware
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topology and reports the latency that the modeled hardware would deliver.
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This isolation is deliberate: it lets us study algorithm-level
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optimizations (how to tile a GEMM, how to schedule a collective, how to
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fuse an attention kernel) and the hardware features that support them,
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without the confound of compiler maturity or framework overhead. The cost
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is that KernBench numbers are \emph{not} E2E latencies; they are the
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achievable-kernel latencies that an ideal software stack would expose.
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\subsection{Execution model}
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\label{sec:exec}
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KernBench is layered along the flow of a request:
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\begin{itemize}
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\item The \textbf{runtime API} is host-facing and
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topology-agnostic---it deploys tensors and launches kernels but knows
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nothing about routing or interconnect.
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\item The \textbf{simulation engine} schedules discrete events, routes
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every request through the modeled graph, and tracks completion via
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correlation IDs.
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\item The \textbf{components} are device-side nodes that model hardware
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behavior: the per-PE blocks (scheduler, DMA, GEMM and vector-math
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engines, TCM, IPCQ), the NoC routers, the HBM controllers, and the
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inter-chiplet links.
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\end{itemize}
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The topology is compiled once at configuration time into an authoritative
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graph of components and links; it is never mutated during a run. Within a
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PE, work is expressed as \emph{composite commands}: a single command
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carries an ordered pipeline of operations
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(\textsf{DMA\_READ} $\rightarrow$ \textsf{FETCH} $\rightarrow$
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\textsf{GEMM}/\textsf{MATH} $\rightarrow$ \textsf{STORE} $\rightarrow$
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\textsf{DMA\_WRITE}) that the PE scheduler tiles and streams. This
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composite mechanism is the substrate for the GEMM optimization
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(\S\ref{sec:gemm}) and, combined with on-PE collectives, for fused
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attention (\S\ref{sec:gqa}). Data and timing are handled in two passes, so
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that a kernel's numeric results and its latency are computed
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consistently but independently.
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\subsection{Latency model and its accuracy}
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\label{sec:latency}
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KernBench obeys a set of golden invariants that keep its latency numbers
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physically meaningful. End-to-end latency is computed \emph{strictly by
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explicit traversal} over modeled components and links: every routed
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request incurs latency greater than zero, routing is deterministic, and
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every valid request flow has explicit connectivity. There are no hidden
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shortcuts, implicit waits, or magic delays---if a delay exists in the
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result, it came from a scheduled event on a modeled component or link.
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Latency accumulates from three kinds of contributions: per-node fixed
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overheads (each component carries an \texttt{overhead\_ns}), per-link
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transfer time, and per-service occupancy. The interconnect is modeled at
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fine granularity. Each directed link serializes traffic through a
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bandwidth-limited FIFO, so a busy link delays later flits. Payloads are
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decomposed into fixed-size flits (default \SI{256}{\byte} bursts) that
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arrive at $\text{prop} + \text{flit\_bytes}/\text{bw}$ intervals, so link
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bandwidth throttles arrival rate rather than being applied as a lump sum.
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HBM is modeled with per-pseudo-channel parallelism: a stateless array of
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channel-availability timestamps with address-based channel selection
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captures bank-level concurrency.
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The cost of \emph{issuing} a command is modeled structurally rather than
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with a per-operation calibration table. The PE control processor charges, per command,
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\[
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d_{\text{cmd}} = \textsf{FIXED} + b_{\text{logical}} \cdot R,
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\]
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where $b_{\text{logical}}$ is the command's hardware-logical byte size,
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\textsf{FIXED} captures the fixed per-command cost (queue-tail
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update, completion registration) and $R$ captures the per-byte cost of
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serializing the command descriptor into the scheduler queue. The default
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anchoring (\textsf{FIXED} $=40$ cycles, $R = 0.0625$ cycles/byte, i.e.\
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\SI{16}{\byte\per\cycle}, at \SI{1}{\giga\hertz}) places a typical
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composite at roughly \SI{43}{\nano\second}, and a hard cap on a
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composite's descriptor size prevents the model from rewarding
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arbitrarily large fused commands beyond what real descriptor queues
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accept. The dispatch cost is enabled and tuned per topology; in the
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configurations measured here, command issue is not the bottleneck---data
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movement is---so this term stays small relative to DMA and collective
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time.
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How accurate is all this? The model is precise about the things that
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dominate kernel latency on this class of hardware: link bandwidth
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occupancy and serialization, HBM channel parallelism, flit-level
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streaming, and per-component switching overhead. The GEMM study
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(\S\ref{sec:gemm}) provides a direct check: the measured MAC efficiency
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tracks the analytic (theoretical) efficiency within roughly
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\SIrange{10}{20}{\percent} across a wide range of tile counts, with the
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gap attributable to pipeline fill and DMA effects that the analytic model
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omits. The known simplifications---idealized arbitration, no thermal or
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refresh effects, fixed burst granularity---are the price of a
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deterministic, inspectable model; they bound the absolute accuracy but do
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not distort the \emph{relative} comparisons (tiling A vs.\ B, topology X
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vs.\ Y) that this report is built on.
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\subsection{Modeled hardware configuration}
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\label{sec:hw}
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Table~\ref{tab:hw} summarizes the hardware configuration used for every
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experiment in this report. It is read directly from the simulator's
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topology description; per-experiment workload parameters (matrix shapes,
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collective sizes, sequence lengths) are stated in their respective
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sections rather than here.
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\begin{table}[t]
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\centering
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\caption{Modeled hardware configuration (shared by all experiments).}
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\label{tab:hw}
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\small
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\begin{tabular}{@{}ll@{}}
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\toprule
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\textbf{Parameter} & \textbf{Value} \\
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\midrule
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\multicolumn{2}{@{}l}{\emph{Hierarchy}} \\
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SIPs & 2 (1D ring) \\
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CUBEs per SIP & 16 ($4\times4$ mesh) \\
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PEs per CUBE & 8 (4 corners $\times$ 2) \\
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PEs total & 256 \\
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\midrule
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\multicolumn{2}{@{}l}{\emph{Processing element (PE)}} \\
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GEMM engine peak & \SI{8}{\tera\flop\per\second} (f16) \\
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TCM (on-PE) & \SI{16}{\mega\byte}, \SI{512}{\giga\byte\per\second} R/W \\
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\quad kernel scratch & \SI{1}{\mega\byte} \\
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DMA engines & 1 read + 1 write \\
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CPU / scheduler overhead & \SI{2}{\nano\second} / \SI{1}{\nano\second} \\
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\midrule
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\multicolumn{2}{@{}l}{\emph{Memory (per CUBE)}} \\
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HBM capacity & \SI{48}{\giga\byte} (8 slices) \\
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HBM aggregate BW & \SI{1024}{\giga\byte\per\second} \\
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HBM pseudo-channels & 64 (8 per PE), \SI{32}{\giga\byte\per\second} each \\
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SRAM (shared) & \SI{32}{\mega\byte}, \SI{128}{\giga\byte\per\second} link \\
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HBM burst & \SI{256}{\byte} \\
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\midrule
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\multicolumn{2}{@{}l}{\emph{Interconnect}} \\
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Intra-CUBE NoC link & \SI{256}{\giga\byte\per\second}, \SI{2}{\nano\second}/router \\
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Inter-CUBE (UCIe PHY) & \SI{512}{\giga\byte\per\second}, \SI{8}{\nano\second}, XY routing \\
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Inter-SIP (PCIe) & \SI{768}{\giga\byte\per\second} per endpoint \\
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\midrule
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\multicolumn{2}{@{}l}{\emph{Command-issue cost model (defaults)}} \\
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FIXED per command & 40 cycles \\
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per-byte rate $R$ & 0.0625 cycles/byte (\SI{16}{\byte\per\cycle}) \\
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composite size cap & \SI{1024}{\byte} \\
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\bottomrule
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\end{tabular}
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\end{table}
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\section{GEMM Acceleration via the Composite Command}
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\label{sec:gemm}
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\subsection{Why it is needed}
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GEMM is the compute core of every transformer block---the QKV
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projections, the attention score and context products, and the
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feed-forward matrices are all matrix multiplications. On a tiled
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accelerator a single logical GEMM expands into many hardware tiles, and
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each tile must be read from HBM, fetched into the register file, computed,
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stored, and written back. If every one of those tile-stage steps were an
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independently issued command, two costs would dominate. First, the host
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and the PE control processor would pay a per-command issue overhead
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$O(\text{tiles}\times\text{stages})$ times, which for a deep-$K$ reduction
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is hundreds to thousands of issues. Second, with stages dispatched
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one-at-a-time the scheduler cannot overlap the DMA of the next tile with
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the compute of the current one---the pipeline never fills, and the MAC
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array sits idle waiting for data. The hardware question is therefore: what
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issue mechanism lets a single GEMM saturate the MAC array without drowning
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in command overhead?
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\subsection{Design}
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The answer is the \emph{composite command}. A single command carries the
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ordered tile pipeline
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\[
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\textsf{DMA\_READ}\rightarrow\textsf{FETCH}\rightarrow\textsf{GEMM}
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\rightarrow\textsf{STORE}\rightarrow\textsf{DMA\_WRITE},
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\]
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and the PE scheduler splits the payload into hardware tiles
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(here $32\times64\times32$), emitting one tile token per tile. Subsequent
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stages are reached by \emph{token self-routing} between the on-PE engines,
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so a tile flows DMA\,$\rightarrow$\,fetch\,$\rightarrow$\,GEMM\,$%
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\rightarrow$\,store without returning to the scheduler between stages.
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Because the whole pipeline is described by one command, the issue cost is
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paid once per GEMM rather than once per tile-stage, and the scheduler is
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free to keep every stage busy on different tiles simultaneously---tile
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$i$'s GEMM overlaps tile $i{+}1$'s DMA read. A multi-operation composite
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additionally lets an epilogue (for example a vector-math step) ride the
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same tile loop, firing per $K$-tile, per output tile, or once per kernel
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according to its declared scope; this is what later allows an attention
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kernel to fuse its softmax work into the GEMM pipeline
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(\S\ref{sec:gqa}).
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\subsection{Results}
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We sweep eight GEMM shapes spanning square, tall, wide, and deep-$K$
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geometries, under three operand-staging variants
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(\textsf{ref\_ref}, both operands streamed from HBM; \textsf{load\_ref},
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one operand resident in TCM; \textsf{load\_load}, both resident).
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Figure~\ref{fig:gemm-util} reports MAC utilization and efficiency, and
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Figure~\ref{fig:gemm-stages} breaks the kernel into per-stage engine
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busy time.
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\begin{figure}[t]
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\centering
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\includegraphics[width=\linewidth]{gemm_mac_utilization_theoretical_vs_measured.png}
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\caption{GEMM MAC utilization and efficiency, theoretical vs.\ measured.
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Tile-fill sets the ceiling: under-tile shapes (marked $\ast$) such as
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$M{=}K{=}N{=}32$, $M{=}8$, and $K{=}8$ cannot fill the MAC tile and cap at
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\SI{50}{\percent}, \SI{25}{\percent}, \SI{12.5}{\percent}. For
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tile-filling shapes, efficiency climbs with tile count---from
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\textasciitilde\SI{23}{\percent} at one tile to \textasciitilde%
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\SI{78}{\percent} measured at 48 tiles ($K{=}3072$)---and the measured
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bars track the analytic prediction within
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\SIrange{10}{20}{\percent}.}
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\label{fig:gemm-util}
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\end{figure}
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\begin{figure}[t]
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\centering
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\includegraphics[width=\linewidth]{gemm_stage_breakdown.png}
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\caption{Per-stage engine wall-clock (DMA in, Fetch, GEMM, DMA out) under
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\textsf{load\_ref} staging. For the deep-$K$ shape ($K{=}3072$, 48 tiles)
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the Fetch and GEMM stages are large and comparable
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(\textasciitilde\SI{770}{} and \SI{785}{\nano\second}) while DMA-out is
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negligible---a compute-rich, well-pipelined regime. For the low-reuse
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shape ($M{=}128,K{=}8,N{=}128$) DMA-out grows to
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\textasciitilde\SI{350}{\nano\second} and compute is small---a
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data-movement-bound regime.}
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\label{fig:gemm-stages}
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\end{figure}
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Two regularities stand out. (i) Utilization is governed by how completely
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the problem fills the MAC tile: the three under-tile shapes are hard-capped
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well below \SI{100}{\percent}, independent of how the kernel is issued.
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(ii) Among tile-filling shapes, efficiency is governed by tile count---more
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tiles amortize the one-time pipeline fill and issue cost, so the deep-$K$
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shape reaches \textasciitilde\SI{78}{\percent} of peak while a single-tile
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shape reaches only \textasciitilde\SI{23}{\percent}. The stage breakdown
|
||||
explains why: with 48 tiles the GEMM and Fetch stages overlap and stay
|
||||
busy, whereas the low-reuse shape spends most of its time moving data in
|
||||
and out.
|
||||
|
||||
\subsection{Analysis and meaning}
|
||||
|
||||
The composite command does not manufacture bandwidth or MAC throughput; it
|
||||
removes the two software-shaped obstacles between a GEMM and its hardware
|
||||
roofline. By paying issue cost once per GEMM and chaining tile-stages
|
||||
through token self-routing, it lets the scheduler keep the pipeline full,
|
||||
so compute-rich shapes actually reach the efficiency their arithmetic
|
||||
intensity allows ($\sim$\SI{78}{\percent} measured at 48 tiles), and
|
||||
data-bound shapes actually reach their DMA bound instead of stalling on
|
||||
command overhead. The close agreement between measured and theoretical
|
||||
efficiency (Figure~\ref{fig:gemm-util}) is also the report's primary
|
||||
validation that KernBench's latency model is faithful in the regime that
|
||||
matters. The hardware implication is concrete: a single-command,
|
||||
self-routing tile pipeline is the issue mechanism that makes the MAC array
|
||||
usable, and it is a prerequisite---not a luxury---for the fused attention
|
||||
kernel of \S\ref{sec:gqa}.
|
||||
@@ -0,0 +1,113 @@
|
||||
\section{All-Reduce Acceleration via PE\_IPCQ}
|
||||
\label{sec:allreduce}
|
||||
|
||||
\subsection{Why it is needed}
|
||||
|
||||
Distributing a transformer across devices turns every tensor-parallel
|
||||
layer into a collective: partial results computed on different PEs, CUBEs,
|
||||
and SIPs must be summed and redistributed with an all-reduce. If that
|
||||
collective is handled by the host or by a generic DMA path, three problems
|
||||
appear. The reduction traffic competes with the kernel's own compute DMA
|
||||
on the same links, causing head-of-line blocking; there is no efficient
|
||||
peer-to-peer ring primitive, so data takes extra hops; and the ordering is
|
||||
hard to make deterministic. The hardware question is how to perform
|
||||
collectives \emph{on the device}, overlapped with compute and reproducible
|
||||
run-to-run.
|
||||
|
||||
\subsection{Design}
|
||||
|
||||
KernBench models a dedicated per-PE collective engine, \textbf{PE\_IPCQ}
|
||||
(inter-PE communication queue). It is a control-plane block: it owns the
|
||||
ring-buffer address arithmetic, head/tail pointers, peer-pointer caches,
|
||||
backpressure, and the four-direction (N/S/E/W) neighbor map, with eight
|
||||
ring buffers per PE (four directions $\times$ \{tx, rx\}). Crucially,
|
||||
PE\_IPCQ does \emph{not} move data itself---it delegates the actual
|
||||
transfer to PE\_DMA, keeping a clean control/data split. To stop
|
||||
collective traffic from blocking compute, PE\_DMA is extended into a
|
||||
two-channel virtual-channel model: \texttt{vc\_compute} carries tile
|
||||
load/store for GEMM and vector math, \texttt{vc\_comm} carries IPCQ sends,
|
||||
each with an independent state machine. The same physical link is shared
|
||||
but progresses in chunks (\SI{256}{\byte}), so a large GEMM DMA does not
|
||||
lock the link end-to-end against a pending reduction. On top of this
|
||||
substrate the collective runs a hierarchical local-reduce / global
|
||||
all-reduce-broadcast schedule across whatever inter-device topology the
|
||||
configuration specifies.
|
||||
|
||||
\subsection{Results}
|
||||
|
||||
Following the milestone-evaluation convention, the collective sweep builds
|
||||
its own six-device (six-SIP, $2\times3$) configurations---distinct from
|
||||
the two-SIP default of Table~\ref{tab:hw}---and measures all-reduce
|
||||
latency as a function of payload size for three inter-device topologies:
|
||||
a 1D ring, a 2D mesh (no wrap), and a 2D torus. Table~\ref{tab:allreduce}
|
||||
and Figure~\ref{fig:allreduce-cmp} report the result.
|
||||
|
||||
\begin{table}[t]
|
||||
\centering
|
||||
\caption{All-reduce latency (ns) across six devices, by topology and
|
||||
per-PE payload. Lower is better; the torus wins at every size.}
|
||||
\label{tab:allreduce}
|
||||
\small
|
||||
\begin{tabular}{@{}rrrr@{}}
|
||||
\toprule
|
||||
\textbf{Bytes/PE} & \textbf{2D mesh} & \textbf{Ring 1D} & \textbf{2D torus} \\
|
||||
\midrule
|
||||
256 & 2667 & 2365 & 1701 \\
|
||||
4{,}096 & 4450 & 4082 & 3038 \\
|
||||
16{,}384 & 8900 & 8217 & 6403 \\
|
||||
65{,}536 & 26705 & 24766 & 19865 \\
|
||||
98{,}304 & 38574 & 35798 & 28840 \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
\begin{figure}[t]
|
||||
\centering
|
||||
\includegraphics[width=\linewidth]{allreduce_comparison.png}
|
||||
\caption{All-reduce latency vs.\ per-PE payload for the three topologies,
|
||||
against the analytic torus model and an external full-system simulator
|
||||
(FSIM) reference. The measured torus tracks the analytic curve within a
|
||||
small constant factor; the FSIM single-device point
|
||||
(\SI{366}{\micro\second}) sits an order of magnitude above the
|
||||
KernBench algorithmic latency, illustrating the difference between an
|
||||
achievable-kernel number and a full end-to-end-stack number.}
|
||||
\label{fig:allreduce-cmp}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[t]
|
||||
\centering
|
||||
\includegraphics[width=\linewidth]{allreduce_buffer_kind.png}
|
||||
\caption{Effect of IPCQ staging-buffer placement (2D torus). At
|
||||
\SI{64}{\kibi\byte}/PE, TCM staging (\SI{19865}{\nano\second}) beats HBM
|
||||
(\SI{23081}{\nano\second}) by \textasciitilde\SI{14}{\percent} and SRAM
|
||||
(\SI{32201}{\nano\second}) by \textasciitilde\SI{38}{\percent}; at small
|
||||
payloads the three are indistinguishable.}
|
||||
\label{fig:allreduce-buf}
|
||||
\end{figure}
|
||||
|
||||
Three findings follow. First, topology matters and the effect grows with
|
||||
size: at \SI{96}{\kilo\byte}/PE the 2D torus is \SI{25}{\percent} faster
|
||||
than the mesh and \SI{19}{\percent} faster than the ring, because its
|
||||
wrap-around links shorten the worst-case reduction path. Second, the
|
||||
measured curves grow smoothly with payload and stay within a small
|
||||
constant factor of the analytic torus model, with the gap reflecting real
|
||||
link serialization that the analytic model idealizes away. Third, where
|
||||
the IPCQ staging buffer lives is a first-order knob: keeping it in on-PE
|
||||
TCM is materially faster than HBM or shared SRAM at large payloads
|
||||
(Figure~\ref{fig:allreduce-buf}).
|
||||
|
||||
\subsection{Analysis and meaning}
|
||||
|
||||
PE\_IPCQ turns the collective from an off-device, contention-prone
|
||||
operation into an on-device primitive whose latency tracks the
|
||||
interconnect's physical limits. The control/data split keeps the engine
|
||||
small while reusing PE\_DMA for movement, and the virtual-channel split is
|
||||
what lets a reduction proceed without stalling the compute DMA that feeds
|
||||
the very GEMMs producing the partials---the same property the fused
|
||||
attention kernel relies on when it interleaves KV reduction with score
|
||||
computation (\S\ref{sec:gqa}). For the hardware roadmap the results argue
|
||||
two things: provisioning wrap-around (torus) inter-device links is worth
|
||||
roughly a \SI{20}{}--\SI{25}{\percent} collective-latency reduction at
|
||||
scale, and giving the IPCQ a fast on-PE staging buffer (TCM) rather than
|
||||
forcing it through HBM or SRAM is worth another \SI{14}{}--%
|
||||
\SI{38}{\percent} at large payloads.
|
||||
@@ -0,0 +1,123 @@
|
||||
\section{Fused Grouped-Query Attention}
|
||||
\label{sec:gqa}
|
||||
|
||||
\subsection{Why it is needed}
|
||||
|
||||
Attention is the 1H focus, and it is where the two preceding optimizations
|
||||
have to come together. Grouped-Query Attention (GQA) shrinks the KV cache
|
||||
by sharing each KV head across a group of query heads (here $h_q=8$ query
|
||||
heads to $h_{kv}=1$ KV head, a group factor $G=8$), which makes decoding
|
||||
feasible at long context but also makes it acutely memory-bound: a decode
|
||||
step processes a single query position ($T_q=1$) against the entire KV
|
||||
history, so its arithmetic intensity is low and its time is dominated by
|
||||
streaming the KV cache out of HBM. FlashAttention-style tiling with an
|
||||
online-softmax merge avoids ever materializing the full score matrix, but
|
||||
realizing it as a fast \emph{fused} kernel needs both building blocks from
|
||||
this report: efficient GEMM issue (\S\ref{sec:gemm}) for the
|
||||
$Q\!\cdot\!K^{\top}$ and $P\!\cdot\!V$ products, and an efficient on-device
|
||||
reduction (\S\ref{sec:allreduce}) for the multi-user and
|
||||
sequence-parallel KV reductions. This section is the capstone: the fused
|
||||
kernel that uses the composite command and PE\_IPCQ at the same time.
|
||||
Multi-head attention (MHA) was studied in prior work and serves here as
|
||||
the established baseline rather than being re-derived.
|
||||
|
||||
\subsection{Design}
|
||||
|
||||
The fused GQA kernel issues its matrix products as scheduler-managed
|
||||
composite commands and keeps the online-softmax merge and the cross-device
|
||||
KV reduction inside the kernel, on PE\_IPCQ. Two kernel families cover the
|
||||
two phases. The \emph{prefill} kernel is head-parallel and rotates the KV
|
||||
shards around an inter-CUBE ring (``Ring KV''). The \emph{decode} kernel
|
||||
is head-replicated with a statically sharded KV cache and reduces partial
|
||||
attention outputs through an M-fold intra-CUBE chain and, for multiple
|
||||
users, a two-level reduce-to-root. Two further primitives make long
|
||||
context practical: a \emph{lazy load} that issues the KV \textsf{DMA\_READ}
|
||||
and returns immediately, auto-waiting only at first use so that KV load
|
||||
overlaps score computation; and per-tile \emph{scratch recycling} that
|
||||
keeps the running softmax accumulators ($m,\ell,O$) in a persistent arena
|
||||
while freeing per-tile temporaries, so the kernel fits the
|
||||
\SI{1}{\mebi\byte} scratch budget across many tiles. A further refinement
|
||||
that restructures the decode step into two stateful composites (a named
|
||||
\textsf{softmax\_merge} recipe) is designed but not yet wired into the
|
||||
measured path; results below reflect the implemented kernel only.
|
||||
|
||||
\subsection{Results}
|
||||
|
||||
We measure four headline panels that vary the user count $C$ and the phase:
|
||||
single- and multi-user prefill ($T_q=4$, $S_{kv}=16$), and single- and
|
||||
multi-user decode ($P=8$ PEs, $S_{kv}=64$ and $128$), all at $d_{\text{head}}=64$
|
||||
and $G=8$. For each panel we harvest end-to-end latency
|
||||
(max event end minus min event start, the same window convention as the
|
||||
GEMM study) together with the per-engine busy time and the operation mix.
|
||||
Figure~\ref{fig:gqa-lat} and Figure~\ref{fig:gqa-break} report the result;
|
||||
the underlying numbers are in Table~\ref{tab:gqa}.
|
||||
|
||||
\begin{table}[t]
|
||||
\centering
|
||||
\caption{Fused GQA per-panel latency and operation mix. Compute (GEMM,
|
||||
MATH) is a tiny fraction of DMA occupancy; IPCQ copies grow with users and
|
||||
PEs.}
|
||||
\label{tab:gqa}
|
||||
\small
|
||||
\begin{tabular}{@{}lrrrr@{}}
|
||||
\toprule
|
||||
\textbf{Panel} & \textbf{Lat.\ (ns)} & \textbf{GEMM} & \textbf{IPCQ} & \textbf{DMA rd} \\
|
||||
\midrule
|
||||
prefill C=1 & 445 & 2 & 0 & 3 \\
|
||||
prefill C=4 (Ring) & 4630 & 32 & 24 & 12 \\
|
||||
decode C=1, P=8 & 3632 & 16 & 21 & 24 \\
|
||||
decode C=4, P=8 & 6693 & 64 & 93 & 96 \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
|
||||
\begin{figure}[t]
|
||||
\centering
|
||||
\includegraphics[width=\linewidth]{gqa_latency_by_panel.png}
|
||||
\caption{Fused GQA end-to-end latency. Latency grows from
|
||||
\SI{445}{\nano\second} (single-user prefill) to \SI{6693}{\nano\second}
|
||||
(four-user decode) as the KV history and the number of participating
|
||||
devices grow.}
|
||||
\label{fig:gqa-lat}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[t]
|
||||
\centering
|
||||
\includegraphics[width=\linewidth]{gqa_op_engine_breakdown.png}
|
||||
\caption{Where the work goes. Left: operation counts---GEMM and IPCQ-copy
|
||||
volume both scale with users and PEs. Right: summed engine occupancy on a
|
||||
log scale---the DMA engine dominates by two to three orders of magnitude
|
||||
over the GEMM and MATH engines in every panel.}
|
||||
\label{fig:gqa-break}
|
||||
\end{figure}
|
||||
|
||||
The dominant observation is in Figure~\ref{fig:gqa-break}: the compute
|
||||
engines are almost idle. The GEMM engine accumulates only
|
||||
\SIrange{2}{33}{\nano\second} of busy time across the panels and the
|
||||
vector-math engine \SIrange{5}{688}{\nano\second}, while the DMA engine
|
||||
accumulates \SIrange{72}{15920}{\nano\second}. Fused GQA, as modeled here,
|
||||
is overwhelmingly data-movement bound. The operation mix shows why the
|
||||
collective machinery matters: IPCQ-copy count rises from zero (single-user
|
||||
prefill) to 93 (four-user decode) as the kernel reduces partial outputs
|
||||
across more PEs and CUBEs, and DMA-read count rises in step as more KV
|
||||
shards are streamed. The PE control-processor dispatch cost registered as
|
||||
zero in this configuration---command issue is simply not on the critical
|
||||
path when data movement is this dominant.
|
||||
|
||||
\subsection{Analysis and meaning}
|
||||
|
||||
These panels are the clearest statement of the codesign thesis in the
|
||||
report. Because the composite command keeps GEMM issue cheap and the MAC
|
||||
array barely occupied, the fused attention kernel's latency is set almost
|
||||
entirely by data movement: streaming the KV cache and reducing partials
|
||||
across devices. That is precisely the cost that the communication-side
|
||||
work targets---PE\_IPCQ for the on-device reduction, the lazy load for
|
||||
load/compute overlap, fast TCM staging and torus links for the reduction
|
||||
itself. In other words, the two enablers are not independent features that
|
||||
happen to appear in the same kernel; the GEMM optimization is what
|
||||
\emph{exposes} the data-movement bottleneck (by removing the compute and
|
||||
issue overhead that would otherwise hide it), and the communication
|
||||
optimization is what \emph{attacks} it. For an attention-dominated decoder
|
||||
the meaningful hardware investments are therefore the ones that move data
|
||||
faster and reduce it on-device---not additional MAC throughput, which this
|
||||
workload cannot use.
|
||||
@@ -0,0 +1,51 @@
|
||||
\section{Discussion: which hardware changes are meaningful}
|
||||
\label{sec:discussion}
|
||||
|
||||
Read together, the three studies point to a consistent ranking of where
|
||||
hardware investment pays off for attention-centric decoding.
|
||||
|
||||
\paragraph{The composite command is foundational, but indirectly.} Its
|
||||
direct effect---driving compute-rich GEMMs to
|
||||
\textasciitilde\SI{78}{\percent} of peak---matters most for the
|
||||
compute-bound parts of a model (the large feed-forward and projection
|
||||
matrices). For attention itself, its more important effect is
|
||||
\emph{diagnostic}: by making issue and compute nearly free, it removes the
|
||||
overhead that would otherwise mask the true bottleneck, and the fused GQA
|
||||
results then show unambiguously that the kernel is data-movement bound.
|
||||
Without a cheap, self-routing issue mechanism we would not be able to tell
|
||||
whether attention is slow because of compute or because of data movement;
|
||||
with it, the answer is clear.
|
||||
|
||||
\paragraph{The communication path is where attention latency actually
|
||||
lives.} Every all-reduce and fused-GQA measurement says the same thing:
|
||||
the limiting resource is moving and reducing data, not multiplying it. That
|
||||
makes the PE\_IPCQ design and the choices around it the highest-value
|
||||
hardware levers for this workload:
|
||||
\begin{itemize}
|
||||
\item \textbf{On-device collectives with a compute/communication
|
||||
virtual-channel split.} Performing the reduction on the device, with
|
||||
\texttt{vc\_comm} separated from \texttt{vc\_compute} so the reduction
|
||||
does not stall the compute DMA, is what lets attention overlap KV
|
||||
movement with score computation at all.
|
||||
\item \textbf{Fast on-PE staging memory.} Keeping the IPCQ buffer in TCM
|
||||
rather than HBM or SRAM is worth \SI{14}{}--\SI{38}{\percent} of
|
||||
collective latency at large payloads---a pure placement decision with a
|
||||
first-order effect.
|
||||
\item \textbf{Wrap-around (torus) inter-device links.} A torus fabric
|
||||
buys \SI{20}{}--\SI{25}{\percent} over a mesh or ring at scale by
|
||||
shortening the worst-case reduction path.
|
||||
\end{itemize}
|
||||
|
||||
\paragraph{Raw MAC throughput is not the constraint for attention.} The
|
||||
GQA panels leave the GEMM and vector-math engines two to three orders of
|
||||
magnitude below the DMA engine in busy time. Adding MAC area would not move
|
||||
decode latency; the workload cannot use it. This is the single most
|
||||
actionable finding for an attention-dominated roadmap.
|
||||
|
||||
\paragraph{Caveats.} These conclusions are achievable-kernel results from a
|
||||
deterministic model, not E2E measurements; absolute numbers carry the
|
||||
model's idealizations (\S\ref{sec:latency}), though the relative rankings
|
||||
that drive the recommendations are robust to them. The headline GQA panels
|
||||
are also at modest scale (up to four users, single SIP), and one designed
|
||||
refinement---the two-composite \textsf{softmax\_merge} decode---is not yet
|
||||
in the measured path. Larger-scale and multi-SIP headline runs are 2H work.
|
||||
@@ -0,0 +1,27 @@
|
||||
\section{Conclusion}
|
||||
\label{sec:conclusion}
|
||||
|
||||
This 1H work set out to make attention-centric LLM kernels fast through
|
||||
hardware--software codesign, and to do so on a platform that isolates
|
||||
algorithm-level behavior from the rest of the software stack. The result is
|
||||
a coherent picture rather than three separate optimizations. A composite
|
||||
command that issues a tiled GEMM as one self-routing pipeline makes the MAC
|
||||
array usable---reaching \textasciitilde\SI{78}{\percent} of peak on
|
||||
compute-rich shapes with measured efficiency tracking theory---and, just as
|
||||
importantly, makes compute cheap enough that the real bottleneck becomes
|
||||
visible. A per-PE on-device collective engine, PE\_IPCQ, turns all-reduce
|
||||
into a primitive whose latency follows the interconnect's physical limits,
|
||||
with topology and staging-memory choices each worth tens of percent. Fused
|
||||
Grouped-Query Attention then combines the two and shows the payoff and the
|
||||
lesson at once: the kernel is data-movement bound, so the optimizations
|
||||
that move and reduce data---not those that add arithmetic---are what
|
||||
determine its speed.
|
||||
|
||||
The practical conclusion for the hardware roadmap is therefore specific.
|
||||
The changes worth keeping are the single-command self-routing GEMM
|
||||
pipeline, the on-device PE\_IPCQ collective with its compute/communication
|
||||
virtual-channel split, fast on-PE staging memory, and wrap-around
|
||||
inter-device links. Additional MAC throughput is not, for this workload, a
|
||||
meaningful investment. KernBench made these conclusions measurable by
|
||||
holding everything except the algorithm and the hardware fixed; the next
|
||||
half extends the same method beyond attention to the rest of the decoder.
|
||||
@@ -0,0 +1,40 @@
|
||||
\section{Future Work --- 2H}
|
||||
\label{sec:future}
|
||||
|
||||
The 1H work covered attention end to end. The natural next step is to
|
||||
complete the decoder and then to ask how compute and data should be
|
||||
distributed for realistic, agentic workloads.
|
||||
|
||||
\paragraph{From attention to the full decoder: FFN and MoE.} A decoder
|
||||
block is attention followed by a feed-forward network (FFN), and in modern
|
||||
models that FFN is increasingly a mixture-of-experts (MoE) layer. The FFN
|
||||
is the compute-rich counterpart to attention---it is where the composite
|
||||
command's MAC-efficiency gains (\S\ref{sec:gemm}) should matter most---so
|
||||
adding it gives a balanced view of a full block instead of its
|
||||
memory-bound half alone. MoE adds a new dimension: a routing step selects a
|
||||
few experts per token, turning the dense FFN GEMM into a sparse, data-
|
||||
dependent dispatch. The open questions are how to issue expert GEMMs as
|
||||
composites under data-dependent token counts, and how to move tokens to
|
||||
experts efficiently---an all-to-all-shaped communication pattern distinct
|
||||
from the all-reduce studied here, and a natural extension of the PE\_IPCQ
|
||||
work.
|
||||
|
||||
\paragraph{Compute and data distribution for full LLM decoding.} With both
|
||||
attention and FFN/MoE in hand, the question becomes where each layer's
|
||||
compute and state should live. Attention is KV-bound and favors keeping the
|
||||
KV cache close to the PEs that consume it; FFN/MoE is compute-bound and
|
||||
favors spreading GEMM work across PEs; MoE routing makes the optimal
|
||||
placement token- and time-dependent. A 2H goal is to use KernBench to
|
||||
explore these placement and parallelization trade-offs---tensor vs.\ expert
|
||||
vs.\ sequence parallelism---under a single, software-stack-independent
|
||||
model, so the interconnect and memory implications of each choice are
|
||||
measured rather than assumed.
|
||||
|
||||
\paragraph{Agentic workloads.} Agentic inference interleaves many
|
||||
short, bursty decode requests with tool use and long shared contexts,
|
||||
which stresses the system differently from a single long generation:
|
||||
context reuse across requests, dynamic batching, and uneven expert load all
|
||||
change how compute and data should be dispersed. Characterizing how total
|
||||
compute and data movement distribute across the SIP/CUBE/PE hierarchy under
|
||||
such workloads---and which of the 1H hardware levers still dominate when the
|
||||
workload is this irregular---is the broader 2H agenda.
|
||||
Reference in New Issue
Block a user