paper: §2 polish + §5 fresh all-reduce data + kernbench probe table

§2 platform:
- Add a "memory-centric AHBM" sentence to the device-and-execution
  intro: each PE is paired with dedicated HBM bandwidth and on-PE
  TCM, so the performance question is about feeding compute from
  locally-attached memory + moving the unavoidable inter-PE traffic
  efficiently. Makes the AHBM character of the platform visible
  before §2.3 starts unpacking the latency model.
- Promote "Congestion and contention modeling" from \paragraph to
  \subsubsection: this is the platform's core differentiator over a
  peak-BW roofline, so it deserves its own heading.
- Rename "Control-plane (issue) cost model" to "Command dispatch
  overhead model" -- describes what it actually charges (the PE_CPU
  paying a fixed + per-byte cost to push a command to one of the
  accelerator engines) without the more abstract "control-plane"
  framing.
- Add a third Accuracy cross-check from kernbench probe: a
  PE→HBM DMA-distance sweep that confirms monotonic hop progression,
  bandwidth saturation matching the per-edge model, and the built-in
  invariants (D2H >= H2D, cross-CUBE best < worst). New
  Table~\ref{tab:probe-pe-dma} reports per-traversal latency and
  utilisation at 32KiB / 1MiB across five hop classes.
- Captured probe output as figures/probe_pe_dma_summary.txt for
  reproducibility.

§5 PE_IPCQ / all-reduce:
- Re-ran milestone-1h-ccl on current sim_engine (post-ADR-0064 Rev2
  and the IPCQ slot-wrap Phase-2 race fix). Updated the topology-
  comparison table and the buffer-kind caption to the fresh raw
  latencies. Headline ratios are preserved:
    torus vs mesh saving at 96 KB/PE: 24.8% (was 24.8%) -> ~25%
    torus vs ring saving at 96 KB/PE: 19.3% (was 19.3%) -> ~19%
    TCM vs HBM saving at 64 KB/PE: 13.4% (was 13.9%) -> ~13%
    TCM vs SRAM saving at 64 KB/PE: 37.2% (was 38.3%) -> ~37%
  The Executive Summary's "up to ~14%" / "up to ~38%" framing stays
  consistent with these post values.

Artifacts refreshed in src/kernbench/benches/1H_milestone_output/:
- ccl/summary.csv + per-topology PNGs + buffer-kind CSV/PNG
- ccl/comparison_mesh_vs_ring_vs_2DTorus_vs_theoretical_vs_fsim.png
- gemm/* (re-run yields identical pe_window structure; PNGs
  refreshed)

Paper figures synced to the fresh artifacts:
- figures/allreduce_comparison.png
- figures/allreduce_buffer_kind.png

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

docs/report/1H-codesign-paper/sections/04-allreduce.tex

@@ -52,11 +52,11 @@ per-PE payload. Lower is better; the torus wins at every size.}
 \toprule
 \textbf{Bytes/PE} & \textbf{2D mesh} & \textbf{Ring 1D} & \textbf{2D torus} \\
 \midrule
-256     & 2667  & 2365  & 1701 \\
-4{,}096  & 4450  & 4082  & 3038 \\
-16{,}384 & 8900  & 8217  & 6403 \\
-65{,}536 & 26705 & 24766 & 19865 \\
-98{,}304 & 38574 & 35798 & 28840 \\
+256     & 4189  & 3883  & 2957 \\
+4{,}096  & 5566  & 5240  & 4031 \\
+16{,}384 & 10016 & 9376  & 7396 \\
+65{,}536 & 27821 & 25925 & 20858 \\
+98{,}304 & 39690 & 36957 & 29833 \\
 \bottomrule
 \end{tabular}
 \end{table}
@@ -78,9 +78,9 @@ achievable-kernel number and a full end-to-end-stack number.}
 \centering
 \includegraphics[width=\linewidth]{allreduce_buffer_kind.png}
 \caption{Effect of IPCQ staging-buffer placement (2D torus). At
-\SI{64}{\kibi\byte}/PE, TCM staging (\SI{19865}{\nano\second}) beats HBM
-(\SI{23081}{\nano\second}) by \textasciitilde\SI{14}{\percent} and SRAM
-(\SI{32201}{\nano\second}) by \textasciitilde\SI{38}{\percent}; at small
+\SI{64}{\kibi\byte}/PE, TCM staging (\SI{20858}{\nano\second}) beats HBM
+(\SI{24074}{\nano\second}) by \textasciitilde\SI{13}{\percent} and SRAM
+(\SI{33194}{\nano\second}) by \textasciitilde\SI{37}{\percent}; at small
 payloads the three are indistinguishable.}
 \label{fig:allreduce-buf}
 \end{figure}