paper: §2 polish + §5 fresh all-reduce data + kernbench probe table
§2 platform:
- Add a "memory-centric AHBM" sentence to the device-and-execution
intro: each PE is paired with dedicated HBM bandwidth and on-PE
TCM, so the performance question is about feeding compute from
locally-attached memory + moving the unavoidable inter-PE traffic
efficiently. Makes the AHBM character of the platform visible
before §2.3 starts unpacking the latency model.
- Promote "Congestion and contention modeling" from \paragraph to
\subsubsection: this is the platform's core differentiator over a
peak-BW roofline, so it deserves its own heading.
- Rename "Control-plane (issue) cost model" to "Command dispatch
overhead model" -- describes what it actually charges (the PE_CPU
paying a fixed + per-byte cost to push a command to one of the
accelerator engines) without the more abstract "control-plane"
framing.
- Add a third Accuracy cross-check from kernbench probe: a
PE→HBM DMA-distance sweep that confirms monotonic hop progression,
bandwidth saturation matching the per-edge model, and the built-in
invariants (D2H >= H2D, cross-CUBE best < worst). New
Table~\ref{tab:probe-pe-dma} reports per-traversal latency and
utilisation at 32KiB / 1MiB across five hop classes.
- Captured probe output as figures/probe_pe_dma_summary.txt for
reproducibility.
§5 PE_IPCQ / all-reduce:
- Re-ran milestone-1h-ccl on current sim_engine (post-ADR-0064 Rev2
and the IPCQ slot-wrap Phase-2 race fix). Updated the topology-
comparison table and the buffer-kind caption to the fresh raw
latencies. Headline ratios are preserved:
torus vs mesh saving at 96 KB/PE: 24.8% (was 24.8%) -> ~25%
torus vs ring saving at 96 KB/PE: 19.3% (was 19.3%) -> ~19%
TCM vs HBM saving at 64 KB/PE: 13.4% (was 13.9%) -> ~13%
TCM vs SRAM saving at 64 KB/PE: 37.2% (was 38.3%) -> ~37%
The Executive Summary's "up to ~14%" / "up to ~38%" framing stays
consistent with these post values.
Artifacts refreshed in src/kernbench/benches/1H_milestone_output/:
- ccl/summary.csv + per-topology PNGs + buffer-kind CSV/PNG
- ccl/comparison_mesh_vs_ring_vs_2DTorus_vs_theoretical_vs_fsim.png
- gemm/* (re-run yields identical pe_window structure; PNGs
refreshed)
Paper figures synced to the fresh artifacts:
- figures/allreduce_comparison.png
- figures/allreduce_buffer_kind.png
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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@@ -0,0 +1,57 @@
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=== H2D Write Latency (IO->HBM, data=32768B) ===
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Case Target Hops Actual Ovhd Drain Wire Ovhd% Drain% Eff.BW BN.BW Util%
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-------------------------------------------------------------------------------------------------------------------
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h2d-1hop cube0.pe0 1 289.53 50.0 256.0 0.18 17.3% 88.4% 113.17 128.0 88.4%
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h2d-2hop cube4.pe0 2 326.04 78.0 256.0 0.20 23.9% 78.5% 100.50 128.0 78.5%
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h2d-3hop cube8.pe0 3 362.56 106.0 256.0 0.20 29.2% 70.6% 90.38 128.0 70.6%
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h2d-4hop cube12.pe0 4 399.06 134.0 256.0 0.21 33.6% 64.1% 82.11 128.0 64.1%
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[v] Monotonic increase: PASS
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BW Saturation (Util% by data size):
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Case 4KB 16KB 64KB 256KB 1MB
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------------------------------------------------------------------
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h2d-1hop 38.9% 71.8% 91.1% 97.6% 99.4%
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h2d-2hop 29.0% 62.1% 86.8% 96.3% 99.1%
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h2d-3hop 23.2% 54.7% 82.8% 95.1% 98.7%
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h2d-4hop 19.3% 48.8% 79.2% 93.8% 98.4%
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=== D2H Read Latency (HBM->IO, data=32768B) ===
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Case Source Hops Actual Ovhd Drain Wire Ovhd% Drain% Eff.BW BN.BW Util%
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-------------------------------------------------------------------------------------------------------------------
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d2h-1hop cube0.pe0 1 571.20 23.0 256.0 0.04 4.0% 44.8% 57.37 128.0 44.8%
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d2h-2hop cube4.pe0 2 635.72 51.0 256.0 0.05 8.0% 40.3% 51.54 128.0 40.3%
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d2h-3hop cube8.pe0 3 700.24 79.0 256.0 0.06 11.3% 36.6% 46.80 128.0 36.6%
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d2h-4hop cube12.pe0 4 764.76 107.0 256.0 0.07 14.0% 33.5% 42.85 128.0 33.5%
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[v] Monotonic increase: PASS
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BW Saturation (Util% by data size):
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Case 4KB 16KB 64KB 256KB 1MB
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------------------------------------------------------------------
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d2h-1hop 9.2% 28.9% 61.9% 86.7% 96.3%
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d2h-2hop 7.8% 25.2% 57.4% 84.4% 95.6%
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d2h-3hop 6.7% 22.4% 53.5% 82.2% 94.9%
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d2h-4hop 5.9% 20.1% 50.2% 80.1% 94.2%
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[v] D2H >= H2D (reverse data path): PASS
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=== PE DMA Latency (pe_dma -> router -> HBM, data=32768B) ===
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Case Target Actual Ovhd Drain Wire Ovhd% Drain% Eff.BW BN.BW Util%
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----------------------------------------------------------------------------------------------------------------------------
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pe-local-hbm c0.pe0->c0.slice0 141.00 2.0 128.0 0.00 1.4% 90.8% 232.40 256.0 90.8%
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pe-same-half-hbm c0.pe0->c0.slice1 147.87 4.0 128.0 0.03 2.7% 86.6% 221.60 256.0 86.6%
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pe-cross-half-hbm c0.pe0->c0.slice4 161.17 10.0 128.0 0.09 6.2% 79.4% 203.31 256.0 79.4%
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pe-cross-cube-hbm-best c0.pe0->c1.slice0 330.52 30.0 256.0 0.01 9.1% 77.5% 99.14 128.0 77.5%
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pe-cross-cube-hbm-worst c0.pe0->c15.slice0 677.12 180.0 256.0 0.06 26.6% 37.8% 48.39 128.0 37.8%
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* Local BN: 256.0 GB/s, Remote BN: 256.0 GB/s
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[v] Cross-cube best < worst: PASS (330.52ns < 677.12ns)
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BW Saturation (Util% by data size):
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Case 4KB 16KB 64KB 256KB 1MB
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------------------------------------------------------------------
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pe-local-hbm 88.9% 97.0% 99.2% 99.8% 100.0%
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pe-same-half-hbm 79.9% 94.1% 98.5% 99.6% 99.9%
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pe-cross-half-hbm 61.3% 86.4% 96.2% 99.0% 99.8%
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pe-cross-cube-hbm-best 51.6% 81.0% 94.5% 98.6% 99.6%
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pe-cross-cube-hbm-worst 15.1% 41.6% 74.0% 91.9% 97.8%
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============================================================
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@@ -8,7 +8,7 @@ execution model it presents to a kernel writer, how its latency model
|
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turns that execution into a number, and the concrete hardware
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configuration used for every experiment that follows.
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\subsection{Why KernBench: source-level kernels without a software stack}
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\subsection{Why KernBench}
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\label{sec:why}
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|
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In a production end-to-end (E2E) stack, kernel performance is entangled
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@@ -55,7 +55,15 @@ physical distance and bandwidth.}
|
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Each CUBE contains eight PEs, shared SRAM, HBM controllers, an
|
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\textsf{M\_CPU} control processor, and an intra-CUBE router mesh
|
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(Fig.~\ref{fig:cube-arch}). Together these components form the
|
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execution substrate for all kernels evaluated in this report.
|
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execution substrate for all kernels evaluated in this report. This
|
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organization reflects the memory-centric nature of AHBM: each PE is
|
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paired with a dedicated slice of HBM bandwidth and local on-PE
|
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storage (TCM), so compute lives next to the data it consumes rather
|
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than fetching it through a far-away memory controller. The platform's
|
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performance question is therefore not ``how many FLOPs can the chip
|
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do'' but ``how well can a kernel keep each compute engine fed from
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its locally-attached memory while moving the unavoidable traffic
|
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between PEs efficiently.''
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\begin{figure}[t]
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\centering
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@@ -195,7 +203,10 @@ collective engines hold the request for their service time before
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releasing it downstream. Each of these is attached to a specific node
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or edge in the graph; together they make up the entire latency budget.
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\paragraph{Congestion: where bottlenecks emerge.} The simulator's
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\subsubsection{Congestion and contention modeling}
|
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\label{sec:congestion}
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|
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The simulator's
|
||||
sharpness comes from how it models contention for those nodes and
|
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edges. \emph{Every directed edge has a FIFO}: an arriving flit takes
|
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its bandwidth-limited transfer time on top of whatever earlier flits
|
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@@ -215,9 +226,11 @@ it reveals where the real bottlenecks form and which hardware levers
|
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actually relieve them---which is exactly the question the codesign
|
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work in this report turns on.
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|
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\paragraph{Control-plane (issue) cost model.} The cost of \emph{issuing}
|
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a command is modelled structurally rather than with a per-operation
|
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calibration table. The PE control processor charges, per command,
|
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\paragraph{Command dispatch overhead model.} The cost incurred by
|
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the \textsf{PE\_CPU} when it dispatches a command to one of the
|
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accelerator engines is modelled structurally rather than with a
|
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per-operation calibration table. The \textsf{PE\_CPU} charges, per
|
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command,
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||||
\[
|
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d_{\text{cmd}} = \textsf{FIXED} + b_{\text{logical}} \cdot R,
|
||||
\]
|
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@@ -267,14 +280,92 @@ hardware--software design trade-offs (tiling A vs.\ B, topology X
|
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vs.\ Y, with vs.\ without composite command, mesh vs.\ torus) that
|
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are the primary objective of this work.
|
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|
||||
A third source of confidence comes from directly probing the
|
||||
simulator's per-traversal behaviour. Running \texttt{kernbench probe}
|
||||
on the modelled topology issues a sequence of PE-to-HBM DMA reads at
|
||||
progressively greater hop distances and reports the per-component
|
||||
overhead, per-edge serialization, and per-PC drain that the model
|
||||
charges (Table~\ref{tab:probe-pe-dma}). Three properties stand out.
|
||||
First, the reported latency increases \emph{monotonically} with hop
|
||||
count---from \SI{141}{\nano\second} at the local HBM slice to
|
||||
\SI{677}{\nano\second} at the worst-case remote-CUBE slice---with the
|
||||
increment per added hop matching the per-router overhead and the
|
||||
UCIe-link cost in Table~\ref{tab:hw}. Second, the bandwidth-saturation
|
||||
curves track the wire's serialization model: at \SI{1}{\mebi\byte}
|
||||
transfers the local PE DMA reaches \SI{100}{\percent} of the per-edge
|
||||
bandwidth limit, while the longest cross-CUBE path saturates at
|
||||
\SI{97.8}{\percent}---exactly the gap that the per-edge propagation
|
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and per-router overhead model would predict. Third, the simulator
|
||||
passes the internal-consistency invariants the probe builds in
|
||||
(monotonic hop progression; D2H reads at least as long as the
|
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equivalent H2D writes because of the reverse-path acknowledgement;
|
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cross-CUBE best less than cross-CUBE worst). These are properties
|
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that hold \emph{only} when the underlying graph traversal, FIFO
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contention, and propagation models are internally
|
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self-consistent---a model error in any of them would surface as a
|
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non-monotonic or under-utilising curve here long before it polluted a
|
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kernel-level measurement.
|
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|
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\begin{table}[t]
|
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\centering
|
||||
\caption{PE\,$\to$\,HBM DMA latency probe at varying hop distances
|
||||
(\SI{32}{\kibi\byte} transfer; output captured from \texttt{kernbench
|
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probe}). \emph{Util\%} is the achieved bandwidth as a fraction of the
|
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path's bottleneck-edge bandwidth.}
|
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\label{tab:probe-pe-dma}
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\small
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\begin{tabular}{@{}lrrr@{}}
|
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\toprule
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Case & Latency~(\si{\nano\second}) & Util\% (\,32\,KiB) & Util\% (\,1\,MiB) \\
|
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\midrule
|
||||
PE\,$\to$\,local HBM & 141.0 & 90.8 & 100.0 \\
|
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PE\,$\to$\,same-half HBM & 147.9 & 86.6 & ~99.9 \\
|
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PE\,$\to$\,cross-half HBM & 161.2 & 79.4 & ~99.8 \\
|
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PE\,$\to$\,cross-CUBE (best) & 330.5 & 77.5 & ~99.6 \\
|
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PE\,$\to$\,cross-CUBE (worst) & 677.1 & 37.8 & ~97.8 \\
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\bottomrule
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\end{tabular}
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\end{table}
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\subsection{Modeled hardware configuration}
|
||||
\label{sec:hw}
|
||||
|
||||
Table~\ref{tab:hw} summarizes the hardware configuration used for
|
||||
every experiment in this report. It is read directly from the
|
||||
simulator's topology description; per-experiment workload parameters
|
||||
(matrix shapes, collective sizes, sequence lengths) are stated in
|
||||
their respective sections rather than here.
|
||||
Table~\ref{tab:hw} summarizes the hardware configuration
|
||||
used throughout this report. The intent of this
|
||||
configuration is not to model a specific product, but to
|
||||
represent a realistic memory-centric accelerator and to
|
||||
provide a consistent baseline for evaluating hardware--
|
||||
software co-design mechanisms.
|
||||
|
||||
The compute capability within each CUBE is provisioned
|
||||
such that inference workloads can effectively saturate
|
||||
the available HBM bandwidth. The aggregate compute
|
||||
throughput is therefore balanced against memory-system
|
||||
bandwidth rather than being intentionally over- or
|
||||
under-provisioned. HBM bandwidth is distributed evenly
|
||||
across the PEs within a CUBE, with each PE responsible
|
||||
for servicing approximately one-eighth of the CUBE's
|
||||
memory bandwidth through its dedicated HBM channels.
|
||||
|
||||
The on-chip interconnect is configured using bandwidth
|
||||
and latency parameters representative of commercially
|
||||
available mesh-network IPs. The goal is not to study a
|
||||
particular NoC implementation, but rather to evaluate
|
||||
kernel behavior under a realistic baseline communication
|
||||
fabric.
|
||||
|
||||
For die-to-die communication, UCIe-A bandwidth
|
||||
characteristics are used as the reference point for
|
||||
inter-CUBE links. Inter-SIP communication is modeled
|
||||
using PCIe-class links. Together, these assumptions
|
||||
provide a representative communication hierarchy for
|
||||
evaluating collective communication and distributed
|
||||
kernel execution.
|
||||
|
||||
Unless otherwise stated, all experiments use this
|
||||
configuration. Workload-specific parameters such as
|
||||
matrix dimensions, sequence lengths, and collective
|
||||
payload sizes are introduced in their respective sections.
|
||||
|
||||
\begin{table}[t]
|
||||
\centering
|
||||
|
||||
@@ -52,11 +52,11 @@ per-PE payload. Lower is better; the torus wins at every size.}
|
||||
\toprule
|
||||
\textbf{Bytes/PE} & \textbf{2D mesh} & \textbf{Ring 1D} & \textbf{2D torus} \\
|
||||
\midrule
|
||||
256 & 2667 & 2365 & 1701 \\
|
||||
4{,}096 & 4450 & 4082 & 3038 \\
|
||||
16{,}384 & 8900 & 8217 & 6403 \\
|
||||
65{,}536 & 26705 & 24766 & 19865 \\
|
||||
98{,}304 & 38574 & 35798 & 28840 \\
|
||||
256 & 4189 & 3883 & 2957 \\
|
||||
4{,}096 & 5566 & 5240 & 4031 \\
|
||||
16{,}384 & 10016 & 9376 & 7396 \\
|
||||
65{,}536 & 27821 & 25925 & 20858 \\
|
||||
98{,}304 & 39690 & 36957 & 29833 \\
|
||||
\bottomrule
|
||||
\end{tabular}
|
||||
\end{table}
|
||||
@@ -78,9 +78,9 @@ achievable-kernel number and a full end-to-end-stack number.}
|
||||
\centering
|
||||
\includegraphics[width=\linewidth]{allreduce_buffer_kind.png}
|
||||
\caption{Effect of IPCQ staging-buffer placement (2D torus). At
|
||||
\SI{64}{\kibi\byte}/PE, TCM staging (\SI{19865}{\nano\second}) beats HBM
|
||||
(\SI{23081}{\nano\second}) by \textasciitilde\SI{14}{\percent} and SRAM
|
||||
(\SI{32201}{\nano\second}) by \textasciitilde\SI{38}{\percent}; at small
|
||||
\SI{64}{\kibi\byte}/PE, TCM staging (\SI{20858}{\nano\second}) beats HBM
|
||||
(\SI{24074}{\nano\second}) by \textasciitilde\SI{13}{\percent} and SRAM
|
||||
(\SI{33194}{\nano\second}) by \textasciitilde\SI{37}{\percent}; at small
|
||||
payloads the three are indistinguishable.}
|
||||
\label{fig:allreduce-buf}
|
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\end{figure}
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+13
-13
@@ -1,13 +1,13 @@
|
||||
buffer_kind,sip_topology,n_sips,n_elem,bytes_per_pe,latency_ns
|
||||
hbm,torus_2d,6,128,256,2120.040000000012
|
||||
hbm,torus_2d,6,1024,2048,2717.2783333333473
|
||||
hbm,torus_2d,6,8192,16384,7315.184999999989
|
||||
hbm,torus_2d,6,32768,65536,23081.26500000037
|
||||
sram,torus_2d,6,128,256,2060.040000000012
|
||||
sram,torus_2d,6,1024,2048,2909.2783333333473
|
||||
sram,torus_2d,6,8192,16384,9523.184999999869
|
||||
sram,torus_2d,6,32768,65536,32201.265000000385
|
||||
tcm,torus_2d,6,128,256,1964.040000000012
|
||||
tcm,torus_2d,6,1024,2048,2477.2783333333473
|
||||
tcm,torus_2d,6,8192,16384,6403.185000000109
|
||||
tcm,torus_2d,6,32768,65536,19865.265000000378
|
||||
buffer_kind,sip_topology,n_sips,n_elem,bytes_per_pe,latency_ns
|
||||
hbm,torus_2d,6,128,256,3113.040000000012
|
||||
hbm,torus_2d,6,1024,2048,3710.2783333333527
|
||||
hbm,torus_2d,6,8192,16384,8308.184999999929
|
||||
hbm,torus_2d,6,32768,65536,24074.26500000037
|
||||
sram,torus_2d,6,128,256,3053.040000000012
|
||||
sram,torus_2d,6,1024,2048,3902.2783333333573
|
||||
sram,torus_2d,6,8192,16384,10516.18499999987
|
||||
sram,torus_2d,6,32768,65536,33194.265000000385
|
||||
tcm,torus_2d,6,128,256,2957.040000000012
|
||||
tcm,torus_2d,6,1024,2048,3470.2783333333527
|
||||
tcm,torus_2d,6,8192,16384,7396.18499999999
|
||||
tcm,torus_2d,6,32768,65536,20858.265000000378
|
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|
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@@ -1,37 +1,37 @@
|
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algorithm,sip_topology,n_sips,n_elem,bytes_per_pe,bytes_per_sip,latency_ns
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,8,16,256,2666.552500000015
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,32,64,1024,2747.7400000000152
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,64,128,2048,2855.990000000018
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,128,256,4096,3072.490000000019
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,512,1024,16384,3337.1133333333582
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,1024,2048,32768,3708.0333333333692
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,2048,4096,65536,4449.873333333393
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,4096,8192,131072,5933.020000000124
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,8192,16384,262144,8900.379999999863
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,16384,32768,524288,14835.099999999224
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,32768,65536,1048576,26704.540000000765
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,49152,98304,1572864,38573.97999999701
|
||||
lrab_hierarchical_allreduce,ring_1d,6,8,16,256,2365.255833333347
|
||||
lrab_hierarchical_allreduce,ring_1d,6,32,64,1024,2436.9433333333473
|
||||
lrab_hierarchical_allreduce,ring_1d,6,64,128,2048,2532.526666666683
|
||||
lrab_hierarchical_allreduce,ring_1d,6,128,256,4096,2723.693333333349
|
||||
lrab_hierarchical_allreduce,ring_1d,6,512,1024,16384,3048.635000000021
|
||||
lrab_hierarchical_allreduce,ring_1d,6,1024,2048,32768,3393.4016666666957
|
||||
lrab_hierarchical_allreduce,ring_1d,6,2048,4096,65536,4082.401666666714
|
||||
lrab_hierarchical_allreduce,ring_1d,6,4096,8192,131072,5458.80166666677
|
||||
lrab_hierarchical_allreduce,ring_1d,6,8192,16384,262144,8216.934999999943
|
||||
lrab_hierarchical_allreduce,ring_1d,6,16384,32768,524288,13733.201666665835
|
||||
lrab_hierarchical_allreduce,ring_1d,6,32768,65536,1048576,24765.73500000064
|
||||
lrab_hierarchical_allreduce,ring_1d,6,49152,98304,1572864,35798.268333331536
|
||||
lrab_hierarchical_allreduce,torus_2d,6,8,16,256,1700.6025000000095
|
||||
lrab_hierarchical_allreduce,torus_2d,6,32,64,1024,1753.2900000000102
|
||||
lrab_hierarchical_allreduce,torus_2d,6,64,128,2048,1823.540000000012
|
||||
lrab_hierarchical_allreduce,torus_2d,6,128,256,4096,1964.040000000012
|
||||
lrab_hierarchical_allreduce,torus_2d,6,512,1024,16384,2196.8183333333463
|
||||
lrab_hierarchical_allreduce,torus_2d,6,1024,2048,32768,2477.2783333333473
|
||||
lrab_hierarchical_allreduce,torus_2d,6,2048,4096,65536,3038.1983333333583
|
||||
lrab_hierarchical_allreduce,torus_2d,6,4096,8192,131072,4159.5050000000665
|
||||
lrab_hierarchical_allreduce,torus_2d,6,8192,16384,262144,6403.185000000109
|
||||
lrab_hierarchical_allreduce,torus_2d,6,16384,32768,524288,10890.5449999995
|
||||
lrab_hierarchical_allreduce,torus_2d,6,32768,65536,1048576,19865.265000000378
|
||||
lrab_hierarchical_allreduce,torus_2d,6,49152,98304,1572864,28839.98500000059
|
||||
algorithm,sip_topology,n_sips,n_elem,bytes_per_pe,bytes_per_sip,latency_ns
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,8,16,256,3782.5525000000202
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,32,64,1024,3863.7400000000207
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,64,128,2048,3971.9900000000216
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,128,256,4096,4188.4900000000225
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,512,1024,16384,4453.113333333365
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,1024,2048,32768,4824.033333333375
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,2048,4096,65536,5565.873333333401
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,4096,8192,131072,7049.020000000062
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,8192,16384,262144,10016.379999999745
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,16384,32768,524288,15951.099999999256
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,32768,65536,1048576,27820.540000000765
|
||||
lrab_hierarchical_allreduce,mesh_2d_no_wrap,6,49152,98304,1572864,39689.97999999693
|
||||
lrab_hierarchical_allreduce,ring_1d,6,8,16,256,3524.2558333333504
|
||||
lrab_hierarchical_allreduce,ring_1d,6,32,64,1024,3595.943333333351
|
||||
lrab_hierarchical_allreduce,ring_1d,6,64,128,2048,3691.5266666666857
|
||||
lrab_hierarchical_allreduce,ring_1d,6,128,256,4096,3882.6933333333527
|
||||
lrab_hierarchical_allreduce,ring_1d,6,512,1024,16384,4207.101666666693
|
||||
lrab_hierarchical_allreduce,ring_1d,6,1024,2048,32768,4550.801666666699
|
||||
lrab_hierarchical_allreduce,ring_1d,6,2048,4096,65536,5240.335000000055
|
||||
lrab_hierarchical_allreduce,ring_1d,6,4096,8192,131072,6617.801666666763
|
||||
lrab_hierarchical_allreduce,ring_1d,6,8192,16384,262144,9375.934999999827
|
||||
lrab_hierarchical_allreduce,ring_1d,6,16384,32768,524288,14892.201666666035
|
||||
lrab_hierarchical_allreduce,ring_1d,6,32768,65536,1048576,25924.735000000648
|
||||
lrab_hierarchical_allreduce,ring_1d,6,49152,98304,1572864,36957.268333330976
|
||||
lrab_hierarchical_allreduce,torus_2d,6,8,16,256,2693.6025000000113
|
||||
lrab_hierarchical_allreduce,torus_2d,6,32,64,1024,2746.290000000012
|
||||
lrab_hierarchical_allreduce,torus_2d,6,64,128,2048,2816.5400000000127
|
||||
lrab_hierarchical_allreduce,torus_2d,6,128,256,4096,2957.040000000012
|
||||
lrab_hierarchical_allreduce,torus_2d,6,512,1024,16384,3189.81833333335
|
||||
lrab_hierarchical_allreduce,torus_2d,6,1024,2048,32768,3470.2783333333527
|
||||
lrab_hierarchical_allreduce,torus_2d,6,2048,4096,65536,4031.1983333333665
|
||||
lrab_hierarchical_allreduce,torus_2d,6,4096,8192,131072,5152.5050000000665
|
||||
lrab_hierarchical_allreduce,torus_2d,6,8192,16384,262144,7396.18499999999
|
||||
lrab_hierarchical_allreduce,torus_2d,6,16384,32768,524288,11883.544999999496
|
||||
lrab_hierarchical_allreduce,torus_2d,6,32768,65536,1048576,20858.265000000378
|
||||
lrab_hierarchical_allreduce,torus_2d,6,49152,98304,1572864,29832.98500000003
|
||||
|
||||
|
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|
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|
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@@ -33,7 +33,7 @@
|
||||
"bytes_hbm": 6144,
|
||||
"arith_intensity": 10.666666666666666,
|
||||
"tile_count_expected": 1,
|
||||
"sim_wall_clock_s": 1.64,
|
||||
"sim_wall_clock_s": 0.297,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -100,7 +100,7 @@
|
||||
"bytes_hbm": 6144,
|
||||
"arith_intensity": 10.666666666666666,
|
||||
"tile_count_expected": 1,
|
||||
"sim_wall_clock_s": 0.696,
|
||||
"sim_wall_clock_s": 0.239,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -167,7 +167,7 @@
|
||||
"bytes_hbm": 6144,
|
||||
"arith_intensity": 10.666666666666666,
|
||||
"tile_count_expected": 1,
|
||||
"sim_wall_clock_s": 0.605,
|
||||
"sim_wall_clock_s": 0.243,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -234,7 +234,7 @@
|
||||
"bytes_hbm": 10240,
|
||||
"arith_intensity": 12.8,
|
||||
"tile_count_expected": 1,
|
||||
"sim_wall_clock_s": 0.599,
|
||||
"sim_wall_clock_s": 0.427,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -301,7 +301,7 @@
|
||||
"bytes_hbm": 10240,
|
||||
"arith_intensity": 12.8,
|
||||
"tile_count_expected": 1,
|
||||
"sim_wall_clock_s": 0.622,
|
||||
"sim_wall_clock_s": 0.336,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -368,7 +368,7 @@
|
||||
"bytes_hbm": 10240,
|
||||
"arith_intensity": 12.8,
|
||||
"tile_count_expected": 1,
|
||||
"sim_wall_clock_s": 0.63,
|
||||
"sim_wall_clock_s": 0.237,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -435,7 +435,7 @@
|
||||
"bytes_hbm": 18432,
|
||||
"arith_intensity": 14.222222222222221,
|
||||
"tile_count_expected": 2,
|
||||
"sim_wall_clock_s": 0.618,
|
||||
"sim_wall_clock_s": 0.322,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -502,7 +502,7 @@
|
||||
"bytes_hbm": 18432,
|
||||
"arith_intensity": 14.222222222222221,
|
||||
"tile_count_expected": 2,
|
||||
"sim_wall_clock_s": 0.642,
|
||||
"sim_wall_clock_s": 0.247,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -569,7 +569,7 @@
|
||||
"bytes_hbm": 18432,
|
||||
"arith_intensity": 14.222222222222221,
|
||||
"tile_count_expected": 2,
|
||||
"sim_wall_clock_s": 0.769,
|
||||
"sim_wall_clock_s": 0.247,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -636,7 +636,7 @@
|
||||
"bytes_hbm": 49152,
|
||||
"arith_intensity": 21.333333333333332,
|
||||
"tile_count_expected": 8,
|
||||
"sim_wall_clock_s": 0.649,
|
||||
"sim_wall_clock_s": 0.359,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -703,7 +703,7 @@
|
||||
"bytes_hbm": 49152,
|
||||
"arith_intensity": 21.333333333333332,
|
||||
"tile_count_expected": 8,
|
||||
"sim_wall_clock_s": 0.639,
|
||||
"sim_wall_clock_s": 0.368,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -770,7 +770,7 @@
|
||||
"bytes_hbm": 49152,
|
||||
"arith_intensity": 21.333333333333332,
|
||||
"tile_count_expected": 8,
|
||||
"sim_wall_clock_s": 0.684,
|
||||
"sim_wall_clock_s": 0.241,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -837,7 +837,7 @@
|
||||
"bytes_hbm": 395264,
|
||||
"arith_intensity": 15.917098445595855,
|
||||
"tile_count_expected": 48,
|
||||
"sim_wall_clock_s": 0.623,
|
||||
"sim_wall_clock_s": 0.318,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -904,7 +904,7 @@
|
||||
"bytes_hbm": 395264,
|
||||
"arith_intensity": 15.917098445595855,
|
||||
"tile_count_expected": 48,
|
||||
"sim_wall_clock_s": 0.763,
|
||||
"sim_wall_clock_s": 0.295,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -971,7 +971,7 @@
|
||||
"bytes_hbm": 395264,
|
||||
"arith_intensity": 15.917098445595855,
|
||||
"tile_count_expected": 48,
|
||||
"sim_wall_clock_s": 0.647,
|
||||
"sim_wall_clock_s": 0.321,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1038,7 +1038,7 @@
|
||||
"bytes_hbm": 36864,
|
||||
"arith_intensity": 7.111111111111111,
|
||||
"tile_count_expected": 8,
|
||||
"sim_wall_clock_s": 0.637,
|
||||
"sim_wall_clock_s": 0.219,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1105,7 +1105,7 @@
|
||||
"bytes_hbm": 36864,
|
||||
"arith_intensity": 7.111111111111111,
|
||||
"tile_count_expected": 8,
|
||||
"sim_wall_clock_s": 0.678,
|
||||
"sim_wall_clock_s": 0.337,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1172,7 +1172,7 @@
|
||||
"bytes_hbm": 36864,
|
||||
"arith_intensity": 7.111111111111111,
|
||||
"tile_count_expected": 8,
|
||||
"sim_wall_clock_s": 0.66,
|
||||
"sim_wall_clock_s": 0.356,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1239,7 +1239,7 @@
|
||||
"bytes_hbm": 36864,
|
||||
"arith_intensity": 7.111111111111111,
|
||||
"tile_count_expected": 16,
|
||||
"sim_wall_clock_s": 0.658,
|
||||
"sim_wall_clock_s": 0.372,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1306,7 +1306,7 @@
|
||||
"bytes_hbm": 36864,
|
||||
"arith_intensity": 7.111111111111111,
|
||||
"tile_count_expected": 16,
|
||||
"sim_wall_clock_s": 0.646,
|
||||
"sim_wall_clock_s": 0.245,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1373,7 +1373,7 @@
|
||||
"bytes_hbm": 36864,
|
||||
"arith_intensity": 7.111111111111111,
|
||||
"tile_count_expected": 16,
|
||||
"sim_wall_clock_s": 0.673,
|
||||
"sim_wall_clock_s": 0.243,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1440,7 +1440,7 @@
|
||||
"bytes_hbm": 1572864,
|
||||
"arith_intensity": 170.66666666666666,
|
||||
"tile_count_expected": 2048,
|
||||
"sim_wall_clock_s": 0.727,
|
||||
"sim_wall_clock_s": 0.357,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1507,7 +1507,7 @@
|
||||
"bytes_hbm": 1572864,
|
||||
"arith_intensity": 170.66666666666666,
|
||||
"tile_count_expected": 2048,
|
||||
"sim_wall_clock_s": 0.707,
|
||||
"sim_wall_clock_s": 0.364,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
@@ -1574,7 +1574,7 @@
|
||||
"bytes_hbm": 1572864,
|
||||
"arith_intensity": 170.66666666666666,
|
||||
"tile_count_expected": 2048,
|
||||
"sim_wall_clock_s": 0.828,
|
||||
"sim_wall_clock_s": 0.239,
|
||||
"engines": {
|
||||
"pe_dma": {
|
||||
"occupancy_ns": 16594.192,
|
||||
|
||||
Reference in New Issue
Block a user