Remove xbar/noc remnants, rule-based cube-view connectors

- Delete xbar.py and noc.py (TwoDMeshNocComponent) — unused since router mesh
- Remove xbar_v1/noc_2d_mesh_v1 from components.yaml
- Fix pe_to_xbar → pe_to_router in routing exclusion set
- Fix xbar_to_hbm_bw_gbs → hbm_to_router_bw_gbs in report.py
- Update all docstrings/comments referencing xbar/bridge → router mesh
- Cube-view connectors: rule-based _connector_points helper
  - PE↔router: single diagonal line (not chevron)
  - UCIe N/S: 45°→horizontal→45°
  - UCIe E/W: 45°→vertical→45°
  - HBM ports: 45°→horizontal→45°

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

src/kernbench/policy/routing/router.py

@@ -81,7 +81,7 @@ class PathRouter:
 
     # Edge kinds excluded from M_CPU DMA adjacency: prevents routing through
     # PE-internal pipeline nodes when computing DMA paths.
-    _MCPU_DMA_EXCLUDE = {"pe_internal", "pe_to_xbar"}
+    _MCPU_DMA_EXCLUDE = {"pe_internal", "pe_to_router"}
 
     _UCIE_KINDS = {"ucie_internal", "ucie_conn_to_router", "router_to_ucie_conn",
                     "ucie_conn_to_noc", "noc_to_ucie_conn", "ucie_mesh",
@@ -124,9 +124,9 @@ class PathRouter:
         return self._run_dijkstra(self._adj_all, m_cpu_id, dst_hbm_id)
 
     def find_memory_path(self, src: str, dst: str) -> list[str]:
-        """Direct memory path: pcie_ep → io_noc → cube → xbar → hbm_ctrl.
+        """Direct memory path: pcie_ep → io_noc → cube → router mesh → hbm_ctrl.
 
-        Uses _adj_mcpu_dma which excludes pe_internal and pe_to_xbar edges,
+        Uses _adj_mcpu_dma which excludes pe_internal and pe_to_router edges,
         preventing routing through PE pipeline nodes.
         """
         return self._run_dijkstra(self._adj_mcpu_dma, src, dst)