Remove xbar/noc remnants, rule-based cube-view connectors

- Delete xbar.py and noc.py (TwoDMeshNocComponent) — unused since router mesh
- Remove xbar_v1/noc_2d_mesh_v1 from components.yaml
- Fix pe_to_xbar → pe_to_router in routing exclusion set
- Fix xbar_to_hbm_bw_gbs → hbm_to_router_bw_gbs in report.py
- Update all docstrings/comments referencing xbar/bridge → router mesh
- Cube-view connectors: rule-based _connector_points helper
  - PE↔router: single diagonal line (not chevron)
  - UCIe N/S: 45°→horizontal→45°
  - UCIe E/W: 45°→vertical→45°
  - HBM ports: 45°→horizontal→45°

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>

src/kernbench/sim_engine/engine.py

@@ -19,9 +19,9 @@ class GraphEngine:
     """simpy-based discrete-event simulation engine.
 
     Request routing:
-      MemoryWrite/Read: pcie_ep → io_noc → cube → xbar → hbm_ctrl (m_cpu bypass)
+      MemoryWrite/Read: pcie_ep → io_noc → cube → router mesh → hbm_ctrl (m_cpu bypass)
       KernelLaunch:     pcie_ep → io_noc → io_cpu → io_noc → cube → m_cpu → PE
-      PeDmaMsg:         pe_dma → xbar → hbm_ctrl (direct probe)
+      PeDmaMsg:         pe_dma → router mesh → hbm_ctrl (direct probe)
 
     Component implementations are DI-injectable via component_overrides (ADR-0007 D3).
     """
@@ -261,7 +261,7 @@ class GraphEngine:
         done.succeed()
 
     def _process_memory_direct(self, key: str, request: Any, done: simpy.Event):
-        """Direct memory path: pcie_ep → io_noc → cube → xbar → hbm_ctrl.
+        """Direct memory path: pcie_ep → io_noc → cube → router mesh → hbm_ctrl.
 
         MemoryWrite: data flows forward (nbytes on wires), drain at hbm_ctrl terminal.
         MemoryRead: command flows forward (nbytes=0), hbm_ctrl sends data back on