Add CHANGES.md, README, update SPEC/ADRs for release 2

- CHANGES.md: detailed changelog for release 1 and 2
- README.md: full project docs with install, probe, run, test usage
- SPEC.md: add ADR-0014~0017 references, update R7 for pcie_ep endpoint
- ADR-0003: update NOC description to reference ADR-0017
- ADR-0004: add HBM efficiency factor (0.8) to BW guarantee contract
- ADR-0014: status Proposed -> Accepted
- ADR-0015: update D4 to M_CPU bypass for Memory R/W, add ADR-0016/0017 links
- ADR-0016 (new): IOChiplet NOC and memory data path
- ADR-0017 (new): Cube NOC 2D mesh architecture
- Fix MD lint warnings (unfenced code blocks) across all docs

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

SPEC.md

@@ -55,6 +55,10 @@ Major architectural decisions are documented in ADRs and referenced by number.
 - ADR-0011: Memory addressing simplification (PA-first)
 - ADR-0012: Host ↔ IO_CPU message schema (PA-first, PE-tagged shards)
 - ADR-0013: Verification strategy and Phase 1 test plan
+- ADR-0014: PE internal execution model (PE_CPU, PE_SCHEDULER, composite commands)
+- ADR-0015: Component port/wire model, BW occupancy, and fabric routing
+- ADR-0016: IOChiplet NOC and memory data path (M_CPU bypass)
+- ADR-0017: Cube NOC 2D mesh architecture (XY routing, contention, attachments)
 
 SPEC MUST remain consistent with accepted ADRs.
 
@@ -165,7 +169,8 @@ Development MUST follow a verification-driven workflow:
 The simulator MUST provide a host-facing runtime API that:
 
 - exposes tensor deployment and kernel execution operations,
-- submits requests only to endpoint components (e.g., IO_CPU),
+- submits requests to endpoint components: PCIE_EP for memory operations
+  (MemoryWrite/Read), IO_CPU for kernel launch,
 - owns host-side tensor handles and allocation metadata as PA shard maps,
 - remains topology-agnostic and does not perform routing or fan-out.