Add CHANGES.md, README, update SPEC/ADRs for release 2

- CHANGES.md: detailed changelog for release 1 and 2
- README.md: full project docs with install, probe, run, test usage
- SPEC.md: add ADR-0014~0017 references, update R7 for pcie_ep endpoint
- ADR-0003: update NOC description to reference ADR-0017
- ADR-0004: add HBM efficiency factor (0.8) to BW guarantee contract
- ADR-0014: status Proposed -> Accepted
- ADR-0015: update D4 to M_CPU bypass for Memory R/W, add ADR-0016/0017 links
- ADR-0016 (new): IOChiplet NOC and memory data path
- ADR-0017 (new): Cube NOC 2D mesh architecture
- Fix MD lint warnings (unfenced code blocks) across all docs

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

docs/adr/ADR-0003-target-system-hierarchy.md

@@ -37,8 +37,10 @@ We model the system hierarchy explicitly:
   - HBM + memory controller (HBM_CTRL)
   - XBAR (top/bottom): HBM pseudo-channel crossbar, PE's dedicated path to HBM
   - Bridge (left/right): connects XBAR.top ↔ XBAR.bottom for cross-half HBM access
-  - NOC: distributed on-die fabric spanning the entire cube (distance modeled as 0);
-    carries non-HBM traffic including inter-cube (UCIe), command (M_CPU↔PE_CPU), and shared SRAM access
+  - NOC: 2D mesh router grid spanning the entire cube with XY routing and
+    per-segment contention modeling; carries all intra-cube traffic including
+    PE DMA to xbar (HBM), inter-cube (UCIe), command (M_CPU↔PE_CPU), and
+    shared SRAM access. See ADR-0017 for full NOC architecture.
   - Shared SRAM: cube-level shared memory accessible by all PEs via NOC
   - management/control CPU (M_CPU) coordinating PE command distribution and completion aggregation
   - multiple PEs
@@ -62,3 +64,4 @@ We model the system hierarchy explicitly:
 
 - SPEC R3/R5
 - ADR-0005 (diagram views)
+- ADR-0017 (cube NOC 2D mesh architecture)