Add CHANGES.md, README, update SPEC/ADRs for release 2
- CHANGES.md: detailed changelog for release 1 and 2 - README.md: full project docs with install, probe, run, test usage - SPEC.md: add ADR-0014~0017 references, update R7 for pcie_ep endpoint - ADR-0003: update NOC description to reference ADR-0017 - ADR-0004: add HBM efficiency factor (0.8) to BW guarantee contract - ADR-0014: status Proposed -> Accepted - ADR-0015: update D4 to M_CPU bypass for Memory R/W, add ADR-0016/0017 links - ADR-0016 (new): IOChiplet NOC and memory data path - ADR-0017 (new): Cube NOC 2D mesh architecture - Fix MD lint warnings (unfenced code blocks) across all docs Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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@@ -21,8 +21,15 @@ Each PE has a notion of “local HBM” that must guarantee full HBM bandwidth,
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### D2. Local HBM bandwidth guarantee contract
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- Accesses from a PE to its local HBM MUST guarantee full HBM read/write bandwidth
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independent of intervening fabric bandwidth limits.
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- Accesses from a PE to its local HBM MUST guarantee full effective HBM
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read/write bandwidth independent of intervening fabric bandwidth limits.
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- Effective HBM bandwidth = spec bandwidth x efficiency factor.
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The efficiency factor (configured via `hbm_ctrl.attrs.efficiency`, default 0.8)
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models real-world DRAM inefficiencies (refresh cycles, bank conflicts, page
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misses). For example: 256 GB/s spec x 0.8 = 204.8 GB/s effective.
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- The topology builder applies the efficiency factor to xbar-to-hbm edge
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bandwidth at graph construction time, so all downstream routing and latency
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computation uses the effective value.
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- This guarantee is modeled by:
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- a dedicated logical path and/or service model that enforces HBM BW at the PE-local-HBM interaction point,
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- while still incurring non-zero latency along explicitly modeled components.
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@@ -62,3 +69,4 @@ Tests should cover:
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- SPEC R2/R5
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- ADR-0002 (distance/order & explicit bypass)
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- ADR-0017 D7 (PE DMA data paths through NOC to HBM)
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