CCL allreduce: rename to lrab_hierarchical_allreduce + descriptive plots

Rename the intercube all-reduce identity to lrab_hierarchical_allreduce
(module, config key, distributed test) so the name reflects both levels
it implements: LRAB intra-SIP (local reduce to center root + broadcast)
and the hierarchical inter-SIP topology exchange (ring/torus/mesh).
ADR-0032 slug kept as the stable decision id; pure rename, no logic change.

Also in this batch:
- ADR-0032 (EN+KO): document the shipped center-root bidirectional reduce
  (doc was stale corner-root); annotate ccl.yaml root_cube as a placeholder.
- Rename allreduce + pe2pe latency plots to descriptive, title-matching
  filenames and retitle the in-plot headings; drop overview/overview_log.
- Point the PPTX image refs at the new plot names.

Doc + derived-artifact + rename only; no simulation behavior changed.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

tests/test_ipcq_buffer_kind_latency.py

@@ -81,7 +81,7 @@ def _run_torus_allreduce(
         sub,
         sip_topology="torus_2d",
         n_sips=6,
-        algorithm="intercube_allreduce",
+        algorithm="lrab_hierarchical_allreduce",
         sip_w=3, sip_h=2,
         n_elem_override=n_elem,
     )
@@ -92,7 +92,7 @@ def _run_torus_allreduce(
         ccl_cfg = yaml.safe_load(f)
     ccl_cfg.setdefault("defaults", {})["buffer_kind"] = buffer_kind
     ccl_cfg.setdefault("algorithms", {}).setdefault(
-        "intercube_allreduce", {},
+        "lrab_hierarchical_allreduce", {},
     )["buffer_kind"] = buffer_kind
     with open(ccl_path, "w") as f:
         yaml.dump(ccl_cfg, f, default_flow_style=False)
@@ -109,7 +109,7 @@ def _run_torus_allreduce(
     ) as ctx:
         result = run_allreduce(
             ctx, engine, spec,
-            algorithm="intercube_allreduce", ccl_yaml=ccl_path,
+            algorithm="lrab_hierarchical_allreduce", ccl_yaml=ccl_path,
         )
         assert result["ok_cubes"] > 0, "allreduce did not validate"