kernbench2

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Author	SHA1	Message	Date
ywkang	6b6e29968a	paper: §2 platform deep-edit + §1 GQA framing + figure regen §2 (KernBench Platform): - Fix Table 2 HBM aggregate BW (1024 → 2048 GB/s); drop stale hbm_total_bw_gbs from topology.yaml (never read by sim_engine) - Split PE_CPU / PE_SCHED fixed-cost row; disambiguate from the 40-cycle command-dispatch FIXED term - §2.2 two-pass: expand to describe Pass 1 timing and Pass 2 data data-correctness path - §2.3 dispatch model: add motivation sentence for the descriptor-size linear form - §2.4 Accuracy: reorder GEMM → All-reduce → Probe → Simplifications; drop FSIM aside (already covered by §4 Fig 5 caption); soften 'every ns' → 'every modeled latency contribution' - §2.5 HW config: add 64 TFLOP/s vs 2048 GB/s (~31 FLOP/byte) balance-point intuition and forward pointer to §5 GQA decode - Fig 1 caption: separate illustrative topology from experimental configuration §1: tighten GQA-as-primary-bandwidth-bottleneck framing. Figures: regenerate SIP / CUBE architecture (SVG sources + PDF + generator scripts). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>	2026-06-16 16:00:23 -07:00
ywkang	7f437a20bd	paper(platform): edit-pass through §2 KernBench Platform done - Reordered §2 subsections to follow the SIP → CUBE → PE → graph flow: Why KernBench → Device and execution model → Latency model → Modeled hardware configuration. Readers now meet the device hierarchy before the graph abstraction that re-uses it. - §2.2 Device and execution model: starts with the SIP/CUBE/PE hierarchy paragraphs (each anchoring fig:sip-arch, fig:cube-arch, fig:pe-arch); then the runtime-API/sim-engine/components bullet list; then the atomic-vs-composite command distinction (corrects the prior over-narrow framing that read every PE command as composite -- atomic single-engine commands exist too, and PE_CPU itself runs control-plane work directly). - §2.3 Latency model: opens with the four-contribution decomposition (per-node overhead, per-edge transmission, drain, queuing delay) and the latency_model schematic; retains existing The hardware as a graph / From graph to DES / Latency contributions / Congestion / Control-plane cost model / Accuracy paragraphs. Accuracy paragraph now closes on KernBench's sufficiency for relative HW/SW design trade-offs given analytic + external-simulator agreement. - New figures and assets: - figures/sip_architecture.pdf (SIP-level graph view) - figures/cube_architecture.pdf (CUBE-level zoom-in) - figures/latency_model.png (conceptual latency-model schematic with per-node / per-edge / drain / queuing-delay colour coding) - figures/pe_architecture.png (carried over) - Source-of-truth generator for the latency schematic: scripts/paper/paper_latency_model_diagram.py (a report-only harness under scripts/paper/ per the /paper isolation rule). - main.tex preamble: \usepackage{tikz} added (kept from prior sequence-diagram draft -- harmless now that the latency model is a PNG; left in to keep paragraph numbering stable). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>	2026-06-15 17:17:19 -07:00

Author

SHA1

Message

Date

ywkang

6b6e29968a

paper: §2 platform deep-edit + §1 GQA framing + figure regen

§2 (KernBench Platform):
- Fix Table 2 HBM aggregate BW (1024 → 2048 GB/s); drop stale
  hbm_total_bw_gbs from topology.yaml (never read by sim_engine)
- Split PE_CPU / PE_SCHED fixed-cost row; disambiguate from the
  40-cycle command-dispatch FIXED term
- §2.2 two-pass: expand to describe Pass 1 timing and Pass 2 data
  data-correctness path
- §2.3 dispatch model: add motivation sentence for the
  descriptor-size linear form
- §2.4 Accuracy: reorder GEMM → All-reduce → Probe →
  Simplifications; drop FSIM aside (already covered by §4 Fig 5
  caption); soften 'every ns' → 'every modeled latency
  contribution'
- §2.5 HW config: add 64 TFLOP/s vs 2048 GB/s (~31 FLOP/byte)
  balance-point intuition and forward pointer to §5 GQA decode
- Fig 1 caption: separate illustrative topology from experimental
  configuration

§1: tighten GQA-as-primary-bandwidth-bottleneck framing.

Figures: regenerate SIP / CUBE architecture (SVG sources + PDF +
generator scripts).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-06-16 16:00:23 -07:00

ywkang

7f437a20bd

paper(platform): edit-pass through §2 KernBench Platform done

- Reordered §2 subsections to follow the SIP → CUBE → PE → graph
  flow: Why KernBench → Device and execution model → Latency model
  → Modeled hardware configuration. Readers now meet the device
  hierarchy before the graph abstraction that re-uses it.
- §2.2 Device and execution model: starts with the SIP/CUBE/PE
  hierarchy paragraphs (each anchoring fig:sip-arch, fig:cube-arch,
  fig:pe-arch); then the runtime-API/sim-engine/components bullet
  list; then the atomic-vs-composite command distinction (corrects
  the prior over-narrow framing that read every PE command as
  composite -- atomic single-engine commands exist too, and PE_CPU
  itself runs control-plane work directly).
- §2.3 Latency model: opens with the four-contribution decomposition
  (per-node overhead, per-edge transmission, drain, queuing delay)
  and the latency_model schematic; retains existing The hardware as
  a graph / From graph to DES / Latency contributions / Congestion
  / Control-plane cost model / Accuracy paragraphs. Accuracy
  paragraph now closes on KernBench's sufficiency for *relative*
  HW/SW design trade-offs given analytic + external-simulator
  agreement.
- New figures and assets:
  - figures/sip_architecture.pdf  (SIP-level graph view)
  - figures/cube_architecture.pdf (CUBE-level zoom-in)
  - figures/latency_model.png      (conceptual latency-model
                                   schematic with per-node /
                                   per-edge / drain / queuing-delay
                                   colour coding)
  - figures/pe_architecture.png    (carried over)
- Source-of-truth generator for the latency schematic:
  scripts/paper/paper_latency_model_diagram.py (a report-only
  harness under scripts/paper/ per the /paper isolation rule).
- main.tex preamble: \usepackage{tikz} added (kept from prior
  sequence-diagram draft -- harmless now that the latency model is
  a PNG; left in to keep paragraph numbering stable).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-06-15 17:17:19 -07:00

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