2 Commits

Author	SHA1	Message	Date
ywkang	81cc32c46b	ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables ... Remove rack_id (4 bits), rename sip_seg→die_id, shift fields to enable 42-bit local_offset (4 TB per die). Define PE_LOCAL/MCPU_LOCAL/CUBE_SRAM sub-unit tables for AHBM dies and IOCPU sub-unit table for IOCHIPLET dies (1 TB window). Supersedes ADR-0031. Also fixes latent VA/PA confusion in pe_dma pipeline DMA path where virtual addresses were decoded as physical addresses without MMU translation — previously masked by coincidental bit-position alignment. 529 passed (+6 recovered), 10 pre-existing failures unchanged. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>	2026-04-27 15:52:29 -07:00
ywkang	95d583ef9f	Add Phase 1→Phase 2 e2e data tests + GraphEngine enable_data mode ... GraphEngine(enable_data=True): - Creates MemoryStore + OpLogger - Injects op_logger into all components - Exposes engine.op_log and engine.memory_store properties E2E tests (test_e2e_data.py): - Engine data mode creates store + logger - Default engine has no store - PeDmaMsg completes successfully with data mode - DataExecutor GEMM accuracy: random f16 matmul with f32 accumulation - DataExecutor chain: GEMM → exp correctness - DataExecutor verify API: pass/fail per tensor - MemoryStore snapshot isolation between Phase 1 and Phase 2 382 tests passing. Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>	2026-04-08 23:49:28 -07:00