 ywkang
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95d583ef9f
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Add Phase 1→Phase 2 e2e data tests + GraphEngine enable_data mode
GraphEngine(enable_data=True):
- Creates MemoryStore + OpLogger
- Injects op_logger into all components
- Exposes engine.op_log and engine.memory_store properties
E2E tests (test_e2e_data.py):
- Engine data mode creates store + logger
- Default engine has no store
- PeDmaMsg completes successfully with data mode
- DataExecutor GEMM accuracy: random f16 matmul with f32 accumulation
- DataExecutor chain: GEMM → exp correctness
- DataExecutor verify API: pass/fail per tensor
- MemoryStore snapshot isolation between Phase 1 and Phase 2
382 tests passing.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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2026-04-08 23:49:28 -07:00 |
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ywkang
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eb792e6212
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Remove xbar/noc remnants, rule-based cube-view connectors
- Delete xbar.py and noc.py (TwoDMeshNocComponent) — unused since router mesh
- Remove xbar_v1/noc_2d_mesh_v1 from components.yaml
- Fix pe_to_xbar → pe_to_router in routing exclusion set
- Fix xbar_to_hbm_bw_gbs → hbm_to_router_bw_gbs in report.py
- Update all docstrings/comments referencing xbar/bridge → router mesh
- Cube-view connectors: rule-based _connector_points helper
- PE↔router: single diagonal line (not chevron)
- UCIe N/S: 45°→horizontal→45°
- UCIe E/W: 45°→vertical→45°
- HBM ports: 45°→horizontal→45°
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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2026-04-06 23:59:12 -07:00 |
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ywkang
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63669f82cb
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Add SIP-level tensor parallelism, component registry YAML, VA offset verification
- DPPolicy: 3-level (sip/cube/pe), unified naming (column_wise/row_wise)
- PE_CPU: auto num_programs from cube shard count
- context.launch(): per-SIP KernelLaunchMsg with local va_base + auto local shape
- deploy_tensor: removed mmus param, MMU mapping is context-only responsibility
- ComponentRegistry: YAML-based lazy loading (components.yaml), impls→builtin rename
- VA offset bench + tests: 2D/1D, standard Triton kernel pattern
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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2026-03-26 01:13:17 -07:00 |
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ywkang
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08812eda58
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Add virtual memory support: PE_MMU, VA allocator, fabric MmuMapMsg
Implement VA/MMU layer (ADR-0011 Phase 1) enabling Triton kernels to use
contiguous virtual addresses on sharded tensors.
Key changes:
- PE_MMU component: hybrid inbox (MmuMapMsg) + sync translate() for PE_DMA
- VirtualAllocator + PEMemAllocator: free-list with coalescing
- MmuMapMsg/MmuUnmapMsg fabric path with SIP-level routing
- DPPolicy-based mapping: replicate=local, sharded=broadcast
- Tensor lifecycle: del + weakref cleanup, context manager
- Rename: TensorHandle.pa→addr, DmaReadCmd.src_pa→src_addr, ctx→torch
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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2026-03-26 00:01:47 -07:00 |
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ywkang
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d75da439c6
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Add probe CLI improvements, D2H read, UCIe/HBM tuning, BW sweep
- Probe CLI: restructured output (tables first, routes below), per-hop
timestamps, split cross-cube into best/worst cases, D2H read section
- UCIe overhead: 1ns -> 8ns per port (16ns per crossing) to fix
cross-cube-best < cross-half latency inversion
- HBM efficiency: added efficiency=0.8 factor to hbm_ctrl, reducing
effective BW from 256 to 204.8 GB/s
- Multi-size BW sweep: saturation tables (4KB-1MB) for all probe cases
- Probe default data size: 4KB -> 32KB for more realistic measurements
- IOChiplet NOC + D2H topology and tests
- NOC mesh, xbar, BW occupancy components and tests
- Cube mesh visualization diagram
278 tests pass.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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2026-03-19 01:16:18 -07:00 |
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ywkang
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6f43807900
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commit - release 1
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2026-03-18 11:47:48 -07:00 |
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