ywkang
998cc85762
Major changes:
PE-level IPCQ infrastructure:
- New PE_IPCQ component: ring-buffer control plane with 4-direction
neighbor mapping, head/tail pointers, backpressure (poll/sleep).
- PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA,
including in-flight data snapshot (D9) and op_log recording at
outbound time for Phase 2 replay correctness.
- IpcqDmaToken piggyback model: data + metadata travel together,
atomic visibility at receiver (invariant I6).
- Credit return fast path: bottleneck-BW latency, no fabric vc_comm.
Phase 2 data execution (ADR-0020 integration):
- op_log extended: DmaWriteCmd now captures src_space/src_addr for
Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time.
- DataExecutor replays dma_write + ipcq_copy in t_start order.
- Engine._flush_data_phase: incremental cursor-based replay after
each engine.wait() so host reads see post-Phase-2 data.
- KernelRunner Phase 1 writes disabled when op_log is active to
prevent stale data from corrupting the MemoryStore snapshot.
TLContext / kernel API:
- tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype),
tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode.
- TensorHandle operator overloading (add/sub/mul/div) via thread-local
active TLContext → MathCmd dispatch through PE_MATH.
- PE-local scratch allocator for math output handles.
- tl.load returns space="hbm" handles for correct Phase 2 addressing.
- Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv.
Unified ccl_allreduce bench (PyTorch-compat host code):
- Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch)
split matching real PyTorch DDP worker pattern.
- torch.distributed facade: init_process_group, get_world_size,
get_rank, get_backend, all_reduce, barrier — only real PyTorch names.
- AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches
kernel via tensor shard metadata (n_elem from shards[0].nbytes).
- world_size derived from topology spec (sips × cubes × pes_per_cube)
with optional algorithm-level override in ccl.yaml.
Tensor API (PyTorch-compat surface):
- Tensor.numpy(): gather-aware (all shards via VA-based addressing).
- Tensor.copy_(source): scatter from host tensor into sharded target.
- RuntimeContext.from_numpy(arr): host-side staging tensor.
- Tensor.data property fixed to use numpy() (was shards[0]-only).
Algorithm modules moved to src/kernbench/ccl/algorithms/:
- ring_allreduce, mesh_allreduce, tree_allreduce, hello_send.
- Each module exports kernel_args(world_size, n_elem) helper.
- ccl.yaml module paths updated to kernbench.ccl.algorithms.*.
Dead code removed:
- 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.).
- _run_ccl_bench greenlet-per-SIP scheduler.
- benches.loader.is_ccl_bench + run_rank detection.
- benches/ccl/ directory.
Tests:
- New test_ccl_allreduce_matrix.py: 7 parametrized cases
(ring×3 buffers, ring 8/16, mesh 4, tree 7).
- New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests.
- Existing tests updated for new import paths + world_size_override.
Docs:
- Korean ccl-author-guide.md and ADR-0023 paths updated.
- New English versions: ccl-author-guide.en.md, ADR-0023.en.md.
502 tests pass.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
428 lines
14 KiB
Python
428 lines
14 KiB
Python
from pathlib import Path
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from kernbench.policy.routing.router import PathRouter
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from kernbench.topology.builder import load_topology
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TOPOLOGY_PATH = Path(__file__).parent.parent / "topology.yaml"
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def _graph():
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return load_topology(TOPOLOGY_PATH)
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# -- Full graph: node counts --------------------------------------------------
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def test_full_graph_node_count():
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g = _graph()
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# 1 switch
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# + 2 SIPs x (1 IO x 23 io_nodes
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# + 16 cubes x (32 routers + 1 hbm_ctrl + 1 m_cpu + 1 sram
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# + 20 ucie (4 ports x (1 port + 4 conn))
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# + 8 PEs x 9 pe_comps)) (ADR-0023: +pe_ipcq)
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# IO: pcie_ep + io_cpu + noc + 4 io_ucie_ports + 4*4 io_ucie_conn = 23
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# cube: 32 + 3 + 20 + 72 = 127
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# = 1 + 2*(23 + 16*127) = 1 + 2*(23+2032) = 1 + 4110 = 4111
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assert len(g.nodes) == 4111
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def test_full_graph_edge_count():
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g = _graph()
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# ADR-0023: +3 IPCQ edges per PE (cpu→ipcq, ipcq→dma, dma→ipcq)
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# 2 SIPs × 16 cubes × 8 PEs × 3 = 768 new edges
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# Cross-SIP routing: +1 reverse pcie_ep→switch edge per SIP = +2
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assert len(g.edges) == 13692
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# -- Full graph: specific nodes exist -----------------------------------------
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def test_system_switch_exists():
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g = _graph()
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assert "fabric.switch0" in g.nodes
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assert g.nodes["fabric.switch0"].kind == "switch"
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assert g.nodes["fabric.switch0"].pos_mm is None # abstract
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def test_io_chiplet_nodes_exist():
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g = _graph()
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for s in range(2):
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assert f"sip{s}.io0.pcie_ep" in g.nodes
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assert f"sip{s}.io0.io_cpu" in g.nodes
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def test_cube_component_nodes_exist():
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g = _graph()
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cp = "sip0.cube0"
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# Core cube components (no more noc, xbar, bridge)
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for name in ("m_cpu", "sram", "hbm_ctrl",
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"ucie-N", "ucie-S", "ucie-E", "ucie-W"):
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assert f"{cp}.{name}" in g.nodes
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# Old nodes must not exist
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for old in ("noc", "xbar_top", "xbar_bot", "bridge.left", "bridge.right"):
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assert f"{cp}.{old}" not in g.nodes
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# Router mesh nodes (32 routers in 6x6 grid minus 4 null holes)
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router_nodes = [n for n in g.nodes if n.startswith(f"{cp}.r")]
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assert len(router_nodes) == 32
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# Spot-check specific routers
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assert f"{cp}.r0c0" in g.nodes
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assert g.nodes[f"{cp}.r0c0"].kind == "noc_router"
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assert f"{cp}.r5c5" in g.nodes
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# Null holes must not exist
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for null_rc in ("r2c2", "r2c3", "r3c2", "r3c3"):
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assert f"{cp}.{null_rc}" not in g.nodes
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# Single hbm_ctrl (no more slices)
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assert g.nodes[f"{cp}.hbm_ctrl"].kind == "hbm_ctrl"
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for s in range(8):
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assert f"{cp}.hbm_ctrl.slice{s}" not in g.nodes
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def test_pe_component_nodes_exist():
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g = _graph()
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for comp in ("pe_cpu", "pe_scheduler", "pe_dma", "pe_gemm", "pe_math", "pe_tcm"):
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assert f"sip0.cube0.pe0.{comp}" in g.nodes
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assert f"sip1.cube15.pe7.{comp}" in g.nodes
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# -- Full graph: positions ----------------------------------------------------
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def test_hbm_ctrl_at_cube_center():
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g = _graph()
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# Single hbm_ctrl per cube; cube0 origin = (0, 0), hbm at (6.5, 7.0)
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node = g.nodes["sip0.cube0.hbm_ctrl"]
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assert node.pos_mm == (6.5, 7.0)
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def test_hbm_ctrl_cube5_position():
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g = _graph()
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# cube5 = col=1, row=1 -> origin = (1*18, 1*15) = (18, 15)
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# hbm_ctrl = (18 + 6.5, 15 + 7.0) = (24.5, 22.0)
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node = g.nodes["sip0.cube5.hbm_ctrl"]
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assert node.pos_mm == (24.5, 22.0)
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def test_ucie_ports_at_cube_edges():
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g = _graph()
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# cube0 origin = (0, 0), cube_w=17, cube_h=14
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# UCIe nodes inset by half-size so edges touch boundary
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assert g.nodes["sip0.cube0.ucie-N"].pos_mm == (8.5, 0.6)
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assert g.nodes["sip0.cube0.ucie-S"].pos_mm == (8.5, 13.4)
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assert g.nodes["sip0.cube0.ucie-W"].pos_mm == (1.0, 7.0)
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assert g.nodes["sip0.cube0.ucie-E"].pos_mm == (16.0, 7.0)
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# -- Full graph: edges --------------------------------------------------------
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def _edge_set(g):
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return {(e.src, e.dst) for e in g.edges}
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def test_inter_cube_ucie_edges():
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es = _edge_set(_graph())
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# cube0 (0,0) E -> cube1 (1,0) W
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assert ("sip0.cube0.ucie-E", "sip0.cube1.ucie-W") in es
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# cube0 (0,0) S -> cube4 (0,1) N
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assert ("sip0.cube0.ucie-S", "sip0.cube4.ucie-N") in es
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def test_io_to_cube_edges():
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es = _edge_set(_graph())
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# io0 connects io_ucie PHYs to cube UCIe ports on N side
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assert ("sip0.io0.ucie-P0", "sip0.cube0.ucie-N") in es
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assert ("sip0.io0.ucie-P3", "sip0.cube3.ucie-N") in es
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def test_switch_to_io_edges():
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es = _edge_set(_graph())
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assert ("fabric.switch0", "sip0.io0.pcie_ep") in es
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assert ("fabric.switch0", "sip1.io0.pcie_ep") in es
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def test_pe_dma_to_router():
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"""PE_DMA connects to its local router (pe_to_router kind)."""
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es = _edge_set(_graph())
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cp = "sip0.cube0"
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# PE0 at r0c0, PE1 at r0c1
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assert (f"{cp}.pe0.pe_dma", f"{cp}.r0c0") in es
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assert (f"{cp}.pe1.pe_dma", f"{cp}.r0c1") in es
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# PE2 at r1c4, PE3 at r1c5
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assert (f"{cp}.pe2.pe_dma", f"{cp}.r1c4") in es
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assert (f"{cp}.pe3.pe_dma", f"{cp}.r1c5") in es
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# PE4 at r4c0, PE5 at r4c1
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assert (f"{cp}.pe4.pe_dma", f"{cp}.r4c0") in es
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assert (f"{cp}.pe5.pe_dma", f"{cp}.r4c1") in es
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# PE6 at r5c4, PE7 at r5c5
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assert (f"{cp}.pe6.pe_dma", f"{cp}.r5c4") in es
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assert (f"{cp}.pe7.pe_dma", f"{cp}.r5c5") in es
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def test_command_path_m_cpu_router_pe_cpu():
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es = _edge_set(_graph())
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cp = "sip0.cube0"
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# m_cpu <-> r1c2 (bidirectional command)
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assert (f"{cp}.m_cpu", f"{cp}.r1c2") in es
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assert (f"{cp}.r1c2", f"{cp}.m_cpu") in es
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# router -> pe_cpu for each PE (command kind)
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assert (f"{cp}.r0c0", f"{cp}.pe0.pe_cpu") in es
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assert (f"{cp}.r5c5", f"{cp}.pe7.pe_cpu") in es
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def test_pe_internal_edges():
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es = _edge_set(_graph())
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pp = "sip0.cube0.pe0"
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assert (f"{pp}.pe_cpu", f"{pp}.pe_scheduler") in es
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assert (f"{pp}.pe_scheduler", f"{pp}.pe_dma") in es
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assert (f"{pp}.pe_scheduler", f"{pp}.pe_gemm") in es
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assert (f"{pp}.pe_scheduler", f"{pp}.pe_math") in es
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assert (f"{pp}.pe_dma", f"{pp}.pe_tcm") in es
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assert (f"{pp}.pe_gemm", f"{pp}.pe_tcm") in es
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assert (f"{pp}.pe_math", f"{pp}.pe_tcm") in es
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def test_hbm_ctrl_connects_all_routers():
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"""HBM_CTRL connects to every router (router_to_hbm / hbm_to_router)."""
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g = _graph()
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es = _edge_set(g)
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cp = "sip0.cube0"
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routers = sorted(n for n in g.nodes if n.startswith(f"{cp}.r"))
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assert len(routers) == 32
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for r in routers:
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assert (r, f"{cp}.hbm_ctrl") in es, f"missing {r}->hbm_ctrl"
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assert (f"{cp}.hbm_ctrl", r) in es, f"missing hbm_ctrl->{r}"
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def test_router_mesh_edges():
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"""Adjacent routers are connected by router_mesh edges."""
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g = _graph()
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edge_kinds = {(e.src, e.dst): e.kind for e in g.edges}
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cp = "sip0.cube0"
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# r0c0 <-> r0c1 (horizontal neighbors)
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assert edge_kinds.get((f"{cp}.r0c0", f"{cp}.r0c1")) == "router_mesh"
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assert edge_kinds.get((f"{cp}.r0c1", f"{cp}.r0c0")) == "router_mesh"
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# r0c0 <-> r1c0 (vertical neighbors)
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assert edge_kinds.get((f"{cp}.r0c0", f"{cp}.r1c0")) == "router_mesh"
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assert edge_kinds.get((f"{cp}.r1c0", f"{cp}.r0c0")) == "router_mesh"
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# -- Views: system ------------------------------------------------------------
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def test_system_view_nodes():
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v = _graph().system_view
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assert "fabric.switch0" in v.nodes
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assert "sip0" in v.nodes
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assert "sip1" in v.nodes
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assert "sip0.io0" in v.nodes
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assert "sip1.io0" in v.nodes
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# -- Views: SIP ---------------------------------------------------------------
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def test_sip_view_cube_count():
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v = _graph().sip_view
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cube_nodes = [n for n in v.nodes if n.startswith("cube")]
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assert len(cube_nodes) == 16
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def test_sip_view_io_chiplets():
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v = _graph().sip_view
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assert "io0" in v.nodes
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def test_sip_view_cube_positions():
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v = _graph().sip_view
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# cube0 (0,0): center = (8.5, 6+7.0) = (8.5, 13.0) [io_margin=6]
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x, y = v.nodes["cube0"].pos_mm
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assert x == 8.5
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assert y == 13.0
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# cube1 (1,0): center = (18+8.5, 13.0) = (26.5, 13.0)
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x1, y1 = v.nodes["cube1"].pos_mm
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assert x1 == 26.5
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assert y1 == 13.0
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# -- Views: cube ---------------------------------------------------------------
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def test_cube_view_has_all_components():
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v = _graph().cube_view
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expected = {"ucie-N", "ucie-S", "ucie-W", "ucie-E",
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"m_cpu", "hbm_ctrl", "sram",
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"pe0", "pe1", "pe2", "pe3", "pe4", "pe5", "pe6", "pe7",
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"r0c0", "r0c1", "r0c2", "r0c3", "r0c4", "r0c5",
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"r1c0", "r1c1", "r1c2", "r1c3", "r1c4", "r1c5",
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"r2c0", "r2c1", "r2c4", "r2c5",
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"r3c0", "r3c1", "r3c4", "r3c5",
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"r4c0", "r4c1", "r4c2", "r4c3", "r4c4", "r4c5",
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"r5c0", "r5c1", "r5c2", "r5c3", "r5c4", "r5c5"}
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# Add UCIe connection nodes (4 ports x 4 connections)
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for port in ("N", "S", "E", "W"):
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for ci in range(4):
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expected.add(f"ucie-{port}.conn{ci}")
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assert set(v.nodes.keys()) == expected
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def test_cube_view_hbm_at_center():
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v = _graph().cube_view
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assert v.nodes["hbm_ctrl"].pos_mm == (6.5, 7.0)
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assert "r0c0" in v.nodes # routers exist in cube view
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assert v.width_mm == 17.0
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assert v.height_mm == 14.0
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def test_cube_view_pe_to_router():
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"""PEs connect to their assigned routers in cube view."""
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v = _graph().cube_view
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ves = {(e.src, e.dst) for e in v.edges}
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pe_router_map = {"pe0": "r0c0", "pe1": "r0c1", "pe2": "r1c4", "pe3": "r1c5",
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"pe4": "r4c0", "pe5": "r4c1", "pe6": "r5c4", "pe7": "r5c5"}
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for pe, router in pe_router_map.items():
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assert (pe, router) in ves, f"{pe} should connect to {router}"
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# -- Views: PE ----------------------------------------------------------------
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def test_pe_view_has_all_components():
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v = _graph().pe_view
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assert set(v.nodes.keys()) == {
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"pe_cpu", "pe_scheduler", "pe_dma", "pe_fetch_store",
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"pe_gemm", "pe_math", "pe_mmu", "pe_tcm", "pe_ipcq",
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}
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def test_pe_view_edges():
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v = _graph().pe_view
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ves = {(e.src, e.dst) for e in v.edges}
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assert ("pe_cpu", "pe_scheduler") in ves
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assert ("pe_scheduler", "pe_dma") in ves
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assert ("pe_scheduler", "pe_gemm") in ves
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assert ("pe_scheduler", "pe_math") in ves
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assert ("pe_dma", "pe_tcm") in ves
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assert ("pe_gemm", "pe_tcm") in ves
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assert ("pe_math", "pe_tcm") in ves
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# -- SRAM ----------------------------------------------------------------------
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def test_sram_node_exists():
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g = _graph()
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assert "sip0.cube0.sram" in g.nodes
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assert g.nodes["sip0.cube0.sram"].kind == "sram"
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def test_sram_to_router_edges():
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es = _edge_set(_graph())
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cp = "sip0.cube0"
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# SRAM connects to router r3c0
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assert (f"{cp}.sram", f"{cp}.r3c0") in es
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assert (f"{cp}.r3c0", f"{cp}.sram") in es
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# -- PE_DMA -> Router (data path) ---------------------------------------------
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def test_pe_dma_to_router_edges():
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es = _edge_set(_graph())
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cp = "sip0.cube0"
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# Each PE DMA connects to its local router
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pe_router_map = {
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0: "r0c0", 1: "r0c1", 2: "r1c4", 3: "r1c5",
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4: "r4c0", 5: "r4c1", 6: "r5c4", 7: "r5c5",
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}
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for i, router in pe_router_map.items():
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assert (f"{cp}.pe{i}.pe_dma", f"{cp}.{router}") in es
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# -- UCIe conn nodes connect to routers (not NOC) -----------------------------
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def test_ucie_noc_reverse_edges():
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"""UCIe ports connect to routers via conn nodes (bidirectional)."""
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es = _edge_set(_graph())
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cp = "sip0.cube1" # non-edge cube to avoid io-cube edges
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for port in ("N", "S", "E", "W"):
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# Each conn has edges: ucie<->conn, conn<->router
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for ci in range(4):
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conn = f"{cp}.ucie-{port}.conn{ci}"
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assert (f"{cp}.ucie-{port}", conn) in es, \
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f"missing ucie-{port}->conn{ci}"
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assert (conn, f"{cp}.ucie-{port}") in es, \
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f"missing conn{ci}->ucie-{port}"
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||
def test_ucie_conn_nodes_exist():
|
||
"""Each UCIe port must have n_connections independent conn nodes."""
|
||
g = _graph()
|
||
cp = "sip0.cube0"
|
||
for port in ("N", "S", "E", "W"):
|
||
for ci in range(4):
|
||
conn_id = f"{cp}.ucie-{port}.conn{ci}"
|
||
assert conn_id in g.nodes, f"missing {conn_id}"
|
||
assert g.nodes[conn_id].kind == "ucie_conn"
|
||
assert g.nodes[conn_id].attrs["overhead_ns"] == 0.0
|
||
|
||
|
||
def test_ucie_conn_edge_bw():
|
||
"""conn<->router edges must have per_connection_bw_gbs (128 GB/s)."""
|
||
g = _graph()
|
||
edge_map = {(e.src, e.dst): e for e in g.edges}
|
||
cp = "sip0.cube0"
|
||
# Check conn0 for each port connects to a router with correct bw
|
||
for port in ("N", "S", "E", "W"):
|
||
for ci in range(4):
|
||
conn_id = f"{cp}.ucie-{port}.conn{ci}"
|
||
# Find the ucie_conn_to_router edge
|
||
conn_edges = [e for e in g.edges
|
||
if e.src == conn_id and e.kind == "ucie_conn_to_router"]
|
||
assert len(conn_edges) == 1, f"expected 1 ucie_conn_to_router from {conn_id}"
|
||
assert conn_edges[0].bw_gbs == 128.0
|
||
|
||
|
||
def test_cross_cube_path_includes_conn():
|
||
"""PE cross-cube path must traverse conn nodes."""
|
||
g = _graph()
|
||
router = PathRouter(g)
|
||
path = router.find_path("sip0.cube0.pe0", "sip0.cube1.hbm_ctrl")
|
||
conn_nodes = [n for n in path if ".conn" in n]
|
||
assert len(conn_nodes) >= 2, f"Expected >=2 conn nodes in path, got {conn_nodes}"
|
||
|
||
|
||
# -- Cube view: edges ---------------------------------------------------------
|
||
|
||
|
||
def test_cube_view_pe_to_router_edges():
|
||
"""All PEs connect to their routers in cube view."""
|
||
v = _graph().cube_view
|
||
ves = {(e.src, e.dst) for e in v.edges}
|
||
pe_router_map = {"pe0": "r0c0", "pe1": "r0c1", "pe2": "r1c4", "pe3": "r1c5",
|
||
"pe4": "r4c0", "pe5": "r4c1", "pe6": "r5c4", "pe7": "r5c5"}
|
||
for pe, router in pe_router_map.items():
|
||
assert (pe, router) in ves, f"{pe} should connect to {router}"
|
||
|
||
|
||
def test_cube_view_sram():
|
||
v = _graph().cube_view
|
||
assert "sram" in v.nodes
|
||
ves = {(e.src, e.dst) for e in v.edges}
|
||
assert ("sram", "r3c0") in ves
|
||
|
||
|
||
def test_cube_view_hbm_router():
|
||
"""Cube view: PE routers connect to hbm_ctrl."""
|
||
v = _graph().cube_view
|
||
ves = {(e.src, e.dst) for e in v.edges}
|
||
assert ("r0c0", "hbm_ctrl") in ves # PE0's router → HBM
|
||
|
||
|
||
def test_cube_view_m_cpu_router():
|
||
"""Cube view: m_cpu connects to its router r1c2."""
|
||
v = _graph().cube_view
|
||
ves = {(e.src, e.dst) for e in v.edges}
|
||
assert ("m_cpu", "r1c2") in ves
|
||
assert ("r1c2", "m_cpu") in ves
|