Files
kernbench2/components.yaml
T
ywkang 998cc85762 Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
Major changes:

PE-level IPCQ infrastructure:
- New PE_IPCQ component: ring-buffer control plane with 4-direction
  neighbor mapping, head/tail pointers, backpressure (poll/sleep).
- PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA,
  including in-flight data snapshot (D9) and op_log recording at
  outbound time for Phase 2 replay correctness.
- IpcqDmaToken piggyback model: data + metadata travel together,
  atomic visibility at receiver (invariant I6).
- Credit return fast path: bottleneck-BW latency, no fabric vc_comm.

Phase 2 data execution (ADR-0020 integration):
- op_log extended: DmaWriteCmd now captures src_space/src_addr for
  Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time.
- DataExecutor replays dma_write + ipcq_copy in t_start order.
- Engine._flush_data_phase: incremental cursor-based replay after
  each engine.wait() so host reads see post-Phase-2 data.
- KernelRunner Phase 1 writes disabled when op_log is active to
  prevent stale data from corrupting the MemoryStore snapshot.

TLContext / kernel API:
- tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype),
  tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode.
- TensorHandle operator overloading (add/sub/mul/div) via thread-local
  active TLContext → MathCmd dispatch through PE_MATH.
- PE-local scratch allocator for math output handles.
- tl.load returns space="hbm" handles for correct Phase 2 addressing.
- Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv.

Unified ccl_allreduce bench (PyTorch-compat host code):
- Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch)
  split matching real PyTorch DDP worker pattern.
- torch.distributed facade: init_process_group, get_world_size,
  get_rank, get_backend, all_reduce, barrier — only real PyTorch names.
- AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches
  kernel via tensor shard metadata (n_elem from shards[0].nbytes).
- world_size derived from topology spec (sips × cubes × pes_per_cube)
  with optional algorithm-level override in ccl.yaml.

Tensor API (PyTorch-compat surface):
- Tensor.numpy(): gather-aware (all shards via VA-based addressing).
- Tensor.copy_(source): scatter from host tensor into sharded target.
- RuntimeContext.from_numpy(arr): host-side staging tensor.
- Tensor.data property fixed to use numpy() (was shards[0]-only).

Algorithm modules moved to src/kernbench/ccl/algorithms/:
- ring_allreduce, mesh_allreduce, tree_allreduce, hello_send.
- Each module exports kernel_args(world_size, n_elem) helper.
- ccl.yaml module paths updated to kernbench.ccl.algorithms.*.

Dead code removed:
- 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.).
- _run_ccl_bench greenlet-per-SIP scheduler.
- benches.loader.is_ccl_bench + run_rank detection.
- benches/ccl/ directory.

Tests:
- New test_ccl_allreduce_matrix.py: 7 parametrized cases
  (ring×3 buffers, ring 8/16, mesh 4, tree 7).
- New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests.
- Existing tests updated for new import paths + world_size_override.

Docs:
- Korean ccl-author-guide.md and ADR-0023 paths updated.
- New English versions: ccl-author-guide.en.md, ADR-0023.en.md.

502 tests pass.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
2026-04-12 19:36:59 -07:00

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2.8 KiB
YAML

# Component implementation registry.
# Maps impl names (used in topology.yaml) to Python class paths.
# Format: impl_name: module.path:ClassName
#
# Naming convention:
# builtin.<name> — built-in implementations
# custom.<name> — user-defined implementations
#
# ── Adding custom components ──────────────────────────────────────────
#
# 1. Create your implementation in:
# src/kernbench/components/custom/<your_component>.py
#
# Your class must inherit from ComponentBase (or PeEngineBase for PE engines).
#
# 2. Register it below under "Custom" with a unique impl name:
# custom.my_pe_cpu: kernbench.components.custom.my_pe_cpu:MyPeCpuComponent
#
# 3. Reference it in topology.yaml:
# pe_cpu: { kind: pe_cpu, impl: custom.my_pe_cpu, attrs: { ... } }
#
# 4. Add unit tests in:
# tests/custom/test_<your_component>.py
#
# External packages also work — use the full module path:
# custom.fast_gemm: my_team.accel.fast_gemm:FastGemmComponent
# ──────────────────────────────────────────────────────────────────────
components:
# Infrastructure
builtin.forwarding: kernbench.components.builtin.forwarding:TransitComponent
builtin.switch: kernbench.components.builtin.forwarding:TransitComponent
builtin.noc: kernbench.components.builtin.forwarding:TransitComponent
builtin.ucie: kernbench.components.builtin.forwarding:TransitComponent
# IO / Host interface
builtin.pcie_ep: kernbench.components.builtin.pcie_ep:PcieEpComponent
builtin.io_cpu: kernbench.components.builtin.io_cpu:IoCpuComponent
# Cube-level
builtin.m_cpu: kernbench.components.builtin.m_cpu:MCpuComponent
builtin.hbm_ctrl: kernbench.components.builtin.hbm_ctrl:HbmCtrlComponent
builtin.sram: kernbench.components.builtin.sram:SramComponent
# PE-level
builtin.pe_cpu: kernbench.components.builtin.pe_cpu:PeCpuComponent
builtin.pe_scheduler: kernbench.components.builtin.pe_scheduler:PeSchedulerComponent
builtin.pe_dma: kernbench.components.builtin.pe_dma:PeDmaComponent
builtin.pe_gemm: kernbench.components.builtin.pe_gemm:PeGemmComponent
builtin.pe_math: kernbench.components.builtin.pe_math:PeMathComponent
builtin.pe_fetch_store: kernbench.components.builtin.pe_fetch_store:PeFetchStoreComponent
builtin.pe_mmu: kernbench.components.builtin.pe_mmu:PeMmuComponent
builtin.pe_tcm: kernbench.components.builtin.pe_tcm:PeTcmComponent
builtin.pe_ipcq: kernbench.components.builtin.pe_ipcq:PeIpcqComponent
# Custom — add your implementations here