ywkang 5fdb6f8797 Latency model: HBM PC striping + chunk-loop drain (ADR-0033) ...

Previous model double-counted slow-upstream paths (e.g., 64KB via UCIe
128 GB/s was ~2x pessimistic). HBM CTRL now distributes bursts across
8 pseudo-channels via global round-robin, with per-chunk commit timing
that pipelines correctly against the bottleneck link's data arrival.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-05-14 21:59:07 -07:00

..

adr

Latency model: HBM PC striping + chunk-loop drain (ADR-0033)

2026-05-14 21:59:07 -07:00

diagrams

Honest measured pipeline efficiency: two timing fixes

2026-05-14 14:19:17 -07:00

ccl-author-guide.en.md

ADR-0026: DPPolicy intra-device only + ShardSpec structural coords

2026-04-14 13:02:19 -07:00

ccl-author-guide.md

ADR-0026: DPPolicy intra-device only + ShardSpec structural coords

2026-04-14 13:02:19 -07:00

di-presentation.md

Add SIP-level tensor parallelism, component registry YAML, VA offset verification

2026-03-26 01:13:17 -07:00

ipcq-dma-codesign-hw.md

IPCQ-DMA co-design HW design doc + fix IPCQ slot BW model

2026-04-28 13:31:02 -07:00

latency-model.md

Add CHANGES.md, README, update SPEC/ADRs for release 2

2026-03-19 01:43:15 -07:00