ywkang
533e699299
Add hardware design document (docs/ipcq-dma-codesign-hw.md) covering PE_IPCQ high-level architecture, simulator verification, proposed HW implementation, and alternatives analysis. Include D2 block diagrams for baseline and proposed PE architectures. Fix IPCQ slot-memory bandwidth parameters to match topology.yaml: SRAM 128→512 GB/s (intrinsic BW, NoC-bottlenecked at 128), HBM 32→256 GB/s (was per-channel, now per-PE aggregate). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Generated Diagrams
This directory contains diagrams generated from topology compilation.
What these files are
- Derived artifacts generated from:
- compiled topology graph
- distance (accumulated latency) metadata
- view/layout rules (ADR-0005)
These files are meant for quick visual inspection and review.
Default outputs
- SIP view:
sip_view.mmd(and/orsip_view.dot) - CUBE view:
cube_view.mmd(and/orcube_view.dot) - PE view:
pe_view.mmd(and/orpe_view.dot)
How to preview
- In VS Code:
- open
.mmdor.mdcontaining Mermaid blocks and use Markdown Preview - for
.dot, use a Graphviz preview extension ordot -Tpng
- open
Notes
- Diagrams are representative and distance-aware by default.
- Instance indices are not required unless debugging asymmetry.
- Outputs should be deterministic for the same topology and rules.