ywkang/kernbench2
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
54fcb7e4bccc8a8b1fc3d7a3620ba0c08a9fb5ad
kernbench2/tests
T
History
mukesh 54fcb7e4bc Add tests/test_emit_ipcq_diagram.py (missed from earlier commit) 
This is the diagram generator that emits ipcq_send_recv.png and
ipcq_two_pe_dma.png (referenced by commit 1e39214 but accidentally
left untracked).

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-04-27 21:42:44 -07:00
..
custom
Add SIP-level tensor parallelism, component registry YAML, VA offset verification
2026-03-26 01:13:17 -07:00
conftest.py
ADR-0023 D9.7: IPCQ slot-memory latency model (TCM/SRAM/HBM)
2026-04-27 21:28:34 -07:00
test_adr0026_dppolicy_intra_device.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_allreduce_buffer_kind_sweep.py
ADR-0023 D9.7: IPCQ slot-memory latency model (TCM/SRAM/HBM)
2026-04-27 21:28:34 -07:00
test_allreduce_multidevice.py
Intercube allreduce: center root + bidirectional reduce
2026-04-27 21:28:58 -07:00
test_bw_occupancy.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_ccl_framework.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_ccl_helpers.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_ccl_install.py
Intercube allreduce: pe0 cube-mesh reduce + multi-SIP ring/torus/mesh
2026-04-16 17:33:42 -07:00
test_ccl_strict_mode.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_ccl_topologies.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_cli_verify_data.py
Add --verify-data CLI flag, Tensor.data property, parallel DataExecutor
2026-04-09 09:34:01 -07:00
test_cli.py
Fix cross-SIP PE_TCM access by scoping deploy to target_device SIP
2026-04-04 18:03:11 -07:00
test_component_registry.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_cross_sip_routing.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_d5_barrier_invariant.py
ADR-0009 D5: chain-aware target_start_ns + zero-byte launch fanout
2026-04-27 15:12:58 -07:00
test_data_executor.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_distributed_intercube_allreduce.py
Intercube allreduce: pe0 cube-mesh reduce + multi-SIP ring/torus/mesh
2026-04-16 17:33:42 -07:00
test_e2e_data.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_e2e_pipeline.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_emit_ipcq_diagram.py
Add tests/test_emit_ipcq_diagram.py (missed from earlier commit)
2026-04-27 21:42:44 -07:00
test_engine.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_intercube_root_center.py
Intercube allreduce: center root + bidirectional reduce
2026-04-27 21:28:58 -07:00
test_intercube_sfr_config.py
ADR-0032 + intra_* opposite directions in IPCQ install
2026-04-27 16:43:01 -07:00
test_iochiplet_noc_d2h.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_ipcq_buffer_kind_latency.py
ADR-0023 D9.7: IPCQ slot-memory latency model (TCM/SRAM/HBM)
2026-04-27 21:28:34 -07:00
test_ipcq_types.py
Fix ADR-0025: IPCQ direction addressing via address-based matching
2026-04-14 00:38:41 -07:00
test_kernel_launch_sync.py
Kernel-launch sync (ADR-0009 D5) and IPCQ drain at inbound (ADR-0023)
2026-04-23 15:30:29 -07:00
test_kernel_runner.py
Implement ADR-0020: 2-pass data execution with greenlet kernel runner
2026-04-08 00:22:44 -07:00
test_memory_store.py
Implement ADR-0020: 2-pass data execution with greenlet kernel runner
2026-04-08 00:22:44 -07:00
test_mmu_component.py
Rename impl names: add builtin. prefix for clear provenance
2026-04-09 00:16:24 -07:00
test_mmu_fabric.py
Wire PE_MMU to router mesh for MmuMapMsg delivery
2026-04-04 18:10:42 -07:00
test_noc_mesh.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_op_log.py
Implement ADR-0020: 2-pass data execution with greenlet kernel runner
2026-04-08 00:22:44 -07:00
test_pe_components.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_pe_dma_ipcq.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_pe_ipcq.py
Fix ADR-0025: IPCQ direction addressing via address-based matching
2026-04-14 00:38:41 -07:00
test_pe_mmu.py
Add virtual memory support: PE_MMU, VA allocator, fabric MmuMapMsg
2026-03-26 00:01:47 -07:00
test_pe_pipeline.py
Add ADR-0021 pipeline tests: self-routing, tiling, overlap
2026-04-08 23:40:19 -07:00
test_pe_to_pe_diagnostic.py
ADR-0023 D9: blocking credit-emit with full-path latency
2026-04-27 15:12:38 -07:00
test_pe_to_pe_latency.py
PE-to-PE latency: drop h5 inter-SIP panel from overview
2026-04-27 16:43:28 -07:00
test_phase_a_components.py
Rename impl names: add builtin. prefix for clear provenance
2026-04-09 00:16:24 -07:00
test_phyaddr.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_probe.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_routing.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_runtime_api_tensor.py
ADR-0026: DPPolicy intra-device only + ShardSpec structural coords
2026-04-14 13:02:19 -07:00
test_sip_parallel.py
ADR-0026: DPPolicy intra-device only + ShardSpec structural coords
2026-04-14 13:02:19 -07:00
test_sip_topology_rectangular.py
Rectangular SIP topology + 6-device allreduce sweep
2026-04-27 15:13:14 -07:00
test_tensor_free.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_tensor.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_tl_ipcq_api.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_topology_compile.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_topology_load.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_topology_visualize.py
Cube-view SVG: detailed topology validation rendering
2026-04-04 22:03:38 -07:00
test_tp_layers.py
ADR-0027: Megatron TP API + worker-wait generalization + mp.spawn
2026-04-14 16:31:13 -07:00
test_tp_mlp.py
ADR-0027: Megatron TP API + worker-wait generalization + mp.spawn
2026-04-14 16:31:13 -07:00
test_tp_parallel_state.py
ADR-0027: Megatron TP API + worker-wait generalization + mp.spawn
2026-04-14 16:31:13 -07:00
test_triton_emu.py
Add PE-level IPCQ collective infra + unified ccl_allreduce bench (ADR-0023)
2026-04-12 19:36:59 -07:00
test_va_allocator.py
Add virtual memory support: PE_MMU, VA allocator, fabric MmuMapMsg
2026-03-26 00:01:47 -07:00
test_va_integration.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00
test_va_offset.py
ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables
2026-04-27 15:52:29 -07:00