ywkang
998cc85762
Major changes:
PE-level IPCQ infrastructure:
- New PE_IPCQ component: ring-buffer control plane with 4-direction
neighbor mapping, head/tail pointers, backpressure (poll/sleep).
- PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA,
including in-flight data snapshot (D9) and op_log recording at
outbound time for Phase 2 replay correctness.
- IpcqDmaToken piggyback model: data + metadata travel together,
atomic visibility at receiver (invariant I6).
- Credit return fast path: bottleneck-BW latency, no fabric vc_comm.
Phase 2 data execution (ADR-0020 integration):
- op_log extended: DmaWriteCmd now captures src_space/src_addr for
Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time.
- DataExecutor replays dma_write + ipcq_copy in t_start order.
- Engine._flush_data_phase: incremental cursor-based replay after
each engine.wait() so host reads see post-Phase-2 data.
- KernelRunner Phase 1 writes disabled when op_log is active to
prevent stale data from corrupting the MemoryStore snapshot.
TLContext / kernel API:
- tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype),
tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode.
- TensorHandle operator overloading (add/sub/mul/div) via thread-local
active TLContext → MathCmd dispatch through PE_MATH.
- PE-local scratch allocator for math output handles.
- tl.load returns space="hbm" handles for correct Phase 2 addressing.
- Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv.
Unified ccl_allreduce bench (PyTorch-compat host code):
- Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch)
split matching real PyTorch DDP worker pattern.
- torch.distributed facade: init_process_group, get_world_size,
get_rank, get_backend, all_reduce, barrier — only real PyTorch names.
- AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches
kernel via tensor shard metadata (n_elem from shards[0].nbytes).
- world_size derived from topology spec (sips × cubes × pes_per_cube)
with optional algorithm-level override in ccl.yaml.
Tensor API (PyTorch-compat surface):
- Tensor.numpy(): gather-aware (all shards via VA-based addressing).
- Tensor.copy_(source): scatter from host tensor into sharded target.
- RuntimeContext.from_numpy(arr): host-side staging tensor.
- Tensor.data property fixed to use numpy() (was shards[0]-only).
Algorithm modules moved to src/kernbench/ccl/algorithms/:
- ring_allreduce, mesh_allreduce, tree_allreduce, hello_send.
- Each module exports kernel_args(world_size, n_elem) helper.
- ccl.yaml module paths updated to kernbench.ccl.algorithms.*.
Dead code removed:
- 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.).
- _run_ccl_bench greenlet-per-SIP scheduler.
- benches.loader.is_ccl_bench + run_rank detection.
- benches/ccl/ directory.
Tests:
- New test_ccl_allreduce_matrix.py: 7 parametrized cases
(ring×3 buffers, ring 8/16, mesh 4, tree 7).
- New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests.
- Existing tests updated for new import paths + world_size_override.
Docs:
- Korean ccl-author-guide.md and ADR-0023 paths updated.
- New English versions: ccl-author-guide.en.md, ADR-0023.en.md.
502 tests pass.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
96 lines
3.1 KiB
Python
96 lines
3.1 KiB
Python
"""Tests for tl.send / tl.recv API (ADR-0023 D4 + D9.5)."""
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from __future__ import annotations
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from typing import Any
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import simpy
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from greenlet import greenlet
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from kernbench.common.ipcq_types import (
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IpcqRecvCmd,
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IpcqRequest,
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IpcqSendCmd,
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)
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from kernbench.triton_emu.tl_context import TLContext
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# ── Command-list mode (no runner) ────────────────────────────────────
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def test_tl_send_command_list_mode():
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tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0)
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tl.send(dir="E", src_addr=0x500, nbytes=64, shape=(8,), dtype="f16")
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cmds = tl.commands
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sends = [c for c in cmds if isinstance(c, IpcqSendCmd)]
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assert len(sends) == 1
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assert sends[0].direction == "E"
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assert sends[0].src_addr == 0x500
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assert sends[0].nbytes == 64
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def test_tl_recv_command_list_mode():
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tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0)
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handle = tl.recv(dir="W", shape=(8,), dtype="f16")
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cmds = tl.commands
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recvs = [c for c in cmds if isinstance(c, IpcqRecvCmd)]
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assert len(recvs) == 1
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assert recvs[0].direction == "W"
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# In command-list mode (no runner), tl.recv returns a placeholder
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# TensorHandle (no actual data movement happens until SimPy)
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assert handle.shape == (8,)
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assert handle.dtype == "f16"
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def test_tl_recv_round_robin_no_dir():
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tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0)
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tl.recv(shape=(8,), dtype="f16")
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cmds = tl.commands
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recvs = [c for c in cmds if isinstance(c, IpcqRecvCmd)]
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assert recvs[0].direction is None
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# ── Runner mode (greenlet) ──────────────────────────────────────────
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class _StubRunner:
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"""Minimal runner that auto-responds to IpcqSendCmd / IpcqRecvCmd."""
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def __init__(self) -> None:
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self.received: list[Any] = []
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def switch_to_simpy(self, cmd: Any) -> Any:
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self.received.append(cmd)
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if isinstance(cmd, IpcqSendCmd):
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return None
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if isinstance(cmd, IpcqRecvCmd):
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# Return a fake slot dict
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return {
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"data": None,
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"src_space": "tcm",
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"src_addr": 0xABCD,
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"direction": cmd.direction or "E",
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"dtype": cmd.dtype,
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"shape": cmd.shape,
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"nbytes": 16,
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}
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return None
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def test_tl_send_runner_mode():
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runner = _StubRunner()
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tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0, runner=runner)
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tl.send(dir="E", src_addr=0x500, nbytes=64, shape=(8,), dtype="f16")
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assert len(runner.received) == 1
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assert isinstance(runner.received[0], IpcqSendCmd)
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def test_tl_recv_runner_mode_returns_handle_with_slot_addr():
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runner = _StubRunner()
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tl = TLContext(pe_id=0, num_programs=4, dispatch_cycles=0, runner=runner)
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h = tl.recv(dir="W", shape=(8,), dtype="f16")
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assert isinstance(runner.received[0], IpcqRecvCmd)
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# The returned TensorHandle's addr should reflect the slot
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assert h.addr == 0xABCD
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assert h.shape == (8,)
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assert h.dtype == "f16"
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