mukesh
f009ba7b1f
Adds the 4-SIP topology referenced by tests/attention/test_attention_8kv_groups_diag.py
(landed in 39fc2e9). Identical to the repo-root topology.yaml except
``system.sips.count: 2 -> 4``, matching the GQA Llama-70B sharding
study's 1 Q-head-per-cube baseline (64 cubes = 8 KV-groups x 8
cubes/group across 4 SIPs).
Opt-in only — only the diag harness and milestone-gqa-llama70b use
this file via env var. The repo-root topology.yaml is unchanged and
continues to drive milestone-1h-ccl / -gemm at their 2-SIP scale.
Without this commit the diag tests pytest.skip on a fresh checkout
("4-SIP topology missing"). With it, step 1 / step 2 / step 3 all run
and pass.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
153 lines
6.8 KiB
YAML
153 lines
6.8 KiB
YAML
# Llama-70B GQA 4-SIP topology — sub-cycle 3 (ADR-0055 + ADR-0056 context).
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#
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# Identical to repo-root topology.yaml except for system.sips.count: 2 → 4,
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# matching the GQA Llama-70B sharding study's TL/TR baseline at 1 Q-head
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# per cube (h_q=64, 8 cubes per KV-group × 8 KV-groups = 64 cubes = 4 SIPs).
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# See:
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# llm_paper_review/notes/GQA_MHA_sharding/scripts/_gen_llama70b_1M_4cases.py
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# lines 17-19 (model dims) and 287-302 (Q/cube scaling configs).
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#
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# Opt-in only — the milestone-gqa-llama70b bench (sub-cycle 4) points at
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# this file via env var. The repo-root topology.yaml is unchanged and
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# continues to drive milestone-1h-ccl / -gemm at their original 2-SIP
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# scale (CLAUDE.md "Surgical Changes").
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system:
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ns_per_mm: 0.01 # wire propagation delay: 10 ps/mm (on-chip silicon)
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sips:
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count: 4
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topology: ring_1d
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components:
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switch: { kind: switch, impl: builtin.switch, attrs: { overhead_ns: 5.0 } }
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links:
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io_ep_to_switch:
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kind: pcie
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bw_gbs_per_ep: 768.0
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distance_mm: 20.0
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sip:
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cube_mesh: { w: 4, h: 4 }
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iochiplet:
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components:
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pcie_ep: { kind: pcie_ep, impl: builtin.pcie_ep, attrs: { overhead_ns: 5.0 } }
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io_cpu: { kind: io_cpu, impl: builtin.io_cpu, attrs: { overhead_ns: 10.0 } }
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io_noc: { kind: io_noc, impl: builtin.forwarding, attrs: { overhead_ns: 0.0 } }
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links:
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pcie_ep_to_noc_bw_gbs: 256.0
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pcie_ep_to_noc_mm: 1.0
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io_cpu_to_noc_bw_gbs: 256.0
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io_cpu_to_noc_mm: 0.5
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ucie:
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overhead_ns: 8.0
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n_connections: 4
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per_connection_bw_gbs: 128.0 # 4 × 128 = 512 GB/s = PHY BW
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noc_to_ucie_mm: 0.5
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instances:
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- id: io0
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place: { side: N, offset_norm: 0.5 }
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ucie: { phy_bw_gbs: 512.0, phys: [P0, P1, P2, P3] }
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cube_ports:
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- { cube: {xy: [0,0]}, cube_side: N, phy: P0, distance_mm: 2.0 }
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- { cube: {xy: [1,0]}, cube_side: N, phy: P1, distance_mm: 2.0 }
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- { cube: {xy: [2,0]}, cube_side: N, phy: P2, distance_mm: 2.0 }
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- { cube: {xy: [3,0]}, cube_side: N, phy: P3, distance_mm: 2.0 }
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links:
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inter_cube_mesh:
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bw_gbs_per_ucie_phy: 512.0
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distance_mm_across_seam: 1.0
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routing: { algo: xy }
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cube:
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geometry:
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cube_mm: { w: 17.0, h: 14.0 }
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hbm_mm: { w: 9.0, h: 5.0 }
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ucie_mm: { size: 2.0 }
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pe_layout:
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corners: [NW, NE, SW, SE] # N corners → top PE rows; S corners → bottom PE rows
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pe_per_corner: 2 # total PEs per cube: 4 * 2 = 8
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pe_template:
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components:
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pe_cpu: { kind: pe_cpu, impl: builtin.pe_cpu, attrs: { overhead_ns: 2.0 } }
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pe_scheduler: { kind: pe_scheduler, impl: builtin.pe_scheduler, attrs: { overhead_ns: 1.0 } }
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pe_dma: { kind: pe_dma, impl: builtin.pe_dma, attrs: { rd_engines: 1, wr_engines: 1 } }
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pe_gemm: { kind: pe_gemm, impl: builtin.pe_gemm, attrs: { overhead_ns: 0.0, shared_resource: accel_slot, peak_tflops_f16: 8.0 } }
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pe_math: { kind: pe_math, impl: builtin.pe_math, attrs: { overhead_ns: 0.0, shared_resource: accel_slot } }
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pe_fetch_store: { kind: pe_fetch_store, impl: builtin.pe_fetch_store, attrs: { overhead_ns: 0.0 } }
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pe_mmu: { kind: pe_mmu, impl: builtin.pe_mmu, attrs: { tlb_overhead_ns: 0.5, page_size: 4096 } }
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pe_tcm: { kind: pe_tcm, impl: builtin.pe_tcm, attrs: { size_mb: 16, read_bw_gbs: 512.0, write_bw_gbs: 512.0, kernel_scratch_mb: 1 } }
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pe_ipcq: { kind: pe_ipcq, impl: builtin.pe_ipcq, attrs: { overhead_ns: 0.0 } }
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links:
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pe_cpu_to_scheduler_mm: 0.5
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scheduler_to_dma_mm: 0.5
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scheduler_to_gemm_mm: 0.5
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scheduler_to_math_mm: 0.5
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scheduler_to_fetch_store_mm: 0.5
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dma_to_tcm_bw_gbs: 512.0
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dma_to_tcm_mm: 0.5
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dma_to_fetch_store_mm: 0.0 # DMA → fetch_store chaining (ADR-0014 D6)
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fetch_store_to_tcm_bw_gbs: 512.0
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fetch_store_to_tcm_mm: 0.0
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fetch_store_to_gemm_mm: 0.0 # fetch → GEMM chaining (ADR-0014 D6)
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fetch_store_to_math_mm: 0.0 # fetch → MATH chaining (ADR-0014 D6)
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gemm_to_fetch_store_mm: 0.0 # GEMM → store chaining (ADR-0014 D6)
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gemm_to_math_mm: 0.0 # GEMM → MATH epilogue chaining (ADR-0014 D6)
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math_to_fetch_store_mm: 0.0 # MATH → store chaining (ADR-0014 D6)
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fetch_store_to_dma_mm: 0.0 # store → DMA writeback chaining (ADR-0014 D6)
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gemm_to_tcm_bw_gbs: 512.0
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gemm_to_tcm_mm: 0.5
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math_to_tcm_bw_gbs: 512.0
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math_to_tcm_mm: 0.5
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cpu_to_ipcq_mm: 0.5 # PE_CPU → PE_IPCQ (ADR-0023)
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ipcq_to_dma_mm: 0.0 # PE_IPCQ → PE_DMA token forwarding (ADR-0023)
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dma_to_ipcq_mm: 0.0 # PE_DMA → PE_IPCQ metadata arrival (ADR-0023)
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memory_map:
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hbm_total_gb_per_cube: 48
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hbm_slices_per_cube: 8
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hbm_total_bw_gbs: 1024.0
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hbm_mapping_mode: n_to_one # one_to_one | n_to_one (ADR-0017 D8)
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hbm_pseudo_channels: 64 # total pseudo channels per cube
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hbm_channels_per_pe: 8 # = pseudo_channels / pes_per_cube
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hbm_channel_bw_gbs: 32.0 # per-channel bandwidth (GB/s)
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components:
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noc_router: { kind: noc_router, impl: builtin.forwarding, attrs: { overhead_ns: 2.0 } }
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m_cpu: { kind: m_cpu, impl: builtin.m_cpu, attrs: { overhead_ns: 5.0 } }
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hbm_ctrl: { kind: hbm_ctrl, impl: builtin.hbm_ctrl, attrs: { capacity: 1, efficiency: 1.0, num_pcs: 8, burst_bytes: 256, switch_penalty_ns: 0.0 } }
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sram: { kind: sram, impl: builtin.sram, attrs: { size_mb: 32, overhead_ns: 2.0 } }
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# Physical placement of non-PE components (mm coordinates)
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placement:
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m_cpu: { pos_mm: [7.5, 3.0] } # top center, below UCIe-N
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sram: { pos_mm: [1.5, 9.0] } # left side, below HBM zone
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ucie:
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decompose: true
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ports: [N, S, E, W]
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overhead_ns: 8.0
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n_connections: 4 # independent NOC↔UCIe connections per port
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per_connection_bw_gbs: 128.0 # BW per connection; 4 × 128 = 512 GB/s = UCIe PHY BW
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links:
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# Router mesh links (ADR-0017 D5)
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router_link_bw_gbs: 256.0 # inter-router XY mesh link BW
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router_overhead_ns: 2.0 # per-router switching overhead
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pe_to_router_bw_gbs: 256.0 # PE_DMA ↔ router (= N × channel_bw)
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hbm_to_router_bw_gbs: 256.0 # HBM_CTRL ↔ router (= N × channel_bw)
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sram_to_router_bw_gbs: 128.0 # SRAM ↔ router
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m_cpu_to_router_mm: 0.0 # M_CPU ↔ router distance
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pe_dma_to_noc_bw_gbs: 256.0 # PE → router BW (= HBM slice BW, no bottleneck)
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noc_to_pe_cpu_mm: 0.0 # router → PE_CPU distance (command path)
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visualization:
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emit_views: [system, sip, cube]
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sip_ids: [0]
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cubes: [0, 9, 15]
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