Files
kernbench2/src/kernbench/components/builtin/pe_tcm.py
T
ywkang 687c98086d ADR housekeeping: category prefixes, lifecycle folders, retroactive 0034-0037
Filename + lifecycle:
- ADR rename to ADR-NNNN-<cat>-title.md with 8 3-letter category prefixes
  (dev / mem / lat / prog / algo / par / api / ver). Numbers stay immutable.
- ADR Lifecycle split into 3 folders, documented in CLAUDE.md Part 2:
  docs/adr/ (Accepted), docs/adr-proposed/ (Proposed/Stub/Draft),
  docs/adr-history/ (Superseded/Merged). Status field gains "Draft" for
  retroactive docs pending verification.

Merges (one ADR per topic, no change-history annotations):
- ADR-0017 absorbs ADR-0019 (Cube NOC + per-PE HBM connectivity, 10 D-items)
- ADR-0014 absorbs ADR-0021 (PE pipeline execution model, 8 D-items incl.
  TileToken self-routing and multi-op composite epilogue scope)
- ADR-0023 absorbs docs/ipcq-dma-codesign-hw.md as new "HW Realization
  Notes (Informative)" section (D16-D23 + Open HW Questions). codesign-hw.md
  deleted; ADR-0019/0021 moved to adr-history with one-line stub status

Retroactive documentation (G4 closures, code-verified):
- ADR-0037 forwarding component (TransitComponent: first-flit overhead,
  serial worker, path-based routing, single impl/multiple names)
- ADR-0036 IO_CPU component (target_start_ns global barrier stamping,
  per-cube fan-out, response aggregation)
- ADR-0035 M_CPU & M_CPU.DMA component (3 fan-out paths, DMA Resources,
  target_start_ns passthrough)
- ADR-0034 HBM controller internal design (per-PC state, address-based
  selection, flit-aware per-flit commit, async finalize, command-only
  fallback path)

Content updates:
- ADR-0010 expanded to full CLI surface (run/probe/web), retitled
  "Command Line Interface and Execution Semantics"
- ADR-0007 D2 rewritten to current state; ADR-0015 supersession notes pruned
- ADR-0005 wrapped in Decision header with D1-D5; ADR-0022 metadata
  block replaced with standard Status header
- ADR-0024 trimmed to rank=SIP launcher essentials (D1-D4);
  ADR-0027 cleaned of supersession history
- ADR-0033 D6 cleanup: address-based PC selection moved out of future-work
  (now documented in ADR-0034 D3); related D1/D3 wording realigned
- Cross-references back-filled in 5 ADRs (G3 gaps closed)

Onboarding docs split:
- docs/onboarding/ created
- moved: hw-architecture-overview.md, latency-model.md, di-presentation.md,
  ccl-author-guide{,.en}.md
- references updated in README, ADR-0023{,.en}, src/kernbench/ccl/__init__.py

Source / test / yaml: ADR-NNNN cross-references in docstrings and YAML
comments updated after the merges (ADR-0021->0014 D6, ADR-0019->0017 D8).
No behavior change.

Tooling:
- tools/verify_adr_lang_pairs.py + tests/test_verify_adr_lang_pairs.py
  (ADR EN/KO pair invariant checker)
- .claude/commands/report.md tracked (/report slash command)
- .gitignore: allow .claude/commands/*.md while keeping settings files ignored

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
2026-05-20 01:15:55 -07:00

83 lines
2.8 KiB
Python

"""PE_TCM: tightly-coupled memory with BW-based access serialization (ADR-0014 D1).
Models scratchpad memory inside the PE. Handles both legacy Transaction forwarding
and TcmRequest from PE_FETCH_STORE for BW-serialized read/write access.
Two channels (read/write) with independent serialization.
Ported from pe_accel TcmBlock timing model.
"""
from __future__ import annotations
from collections.abc import Generator
from dataclasses import dataclass
from typing import TYPE_CHECKING, Any
import simpy
from kernbench.components.base import ComponentBase
if TYPE_CHECKING:
from kernbench.components.context import ComponentContext
from kernbench.topology.types import Node
@dataclass
class TcmRequest:
"""Request to read from or write to TCM (used by PE_FETCH_STORE)."""
direction: str # "read" or "write"
nbytes: int
done: simpy.Event
tag: str = ""
class PeTcmComponent(ComponentBase):
"""PE_TCM: BW-serialized scratchpad memory (ADR-0014 D1).
Dual-channel: read and write can proceed in parallel,
but concurrent reads serialize, concurrent writes serialize.
BW from topology attrs or pe_template links.
"""
def __init__(self, node: Node, ctx: ComponentContext | None = None) -> None:
super().__init__(node, ctx)
self._read_bw: float = float(node.attrs.get("read_bw_gbs", 512.0))
self._write_bw: float = float(node.attrs.get("write_bw_gbs", 512.0))
self._read_res: simpy.Resource | None = None
self._write_res: simpy.Resource | None = None
def start(self, env: simpy.Environment) -> None:
self._read_res = simpy.Resource(env, capacity=1)
self._write_res = simpy.Resource(env, capacity=1)
super().start(env)
def run(self, env: simpy.Environment, nbytes: int) -> Generator:
overhead_ns = float(self.node.attrs.get("overhead_ns", 0.0))
yield env.timeout(overhead_ns)
def _worker(self, env: simpy.Environment) -> Generator:
"""Dispatch TcmRequest (from fetch_store) and Transaction (fabric)."""
while True:
msg: Any = yield self._inbox.get()
if isinstance(msg, TcmRequest):
env.process(self._handle_tcm_request(env, msg))
else:
env.process(self._forward_txn(env, msg))
def _handle_tcm_request(self, env: simpy.Environment, req: TcmRequest) -> Generator:
"""BW-serialized access: acquire channel, apply delay, signal done."""
if req.direction == "write":
res = self._write_res
bw = self._write_bw
else:
res = self._read_res
bw = self._read_bw
assert res is not None
with res.request() as lock:
yield lock
if bw > 0 and req.nbytes > 0:
delay_ns = req.nbytes / bw
yield env.timeout(delay_ns)
req.done.succeed()