ywkang
aaa1cbfaf6
Replaces global round-robin with deterministic address-derived PC
striping:
pc_shift = log2(burst_bytes)
pc_mask = num_pcs - 1
pc = (flit.address >> pc_shift) & pc_mask
Each Transaction carries base_address (HBM byte offset of the first
chunk); each Flit derives its own address as base + i*flit_bytes.
HBM CTRL routes flits to PCs via this formula, replacing the
arrival-order RR pointer. Also splits the is_last wait into an
asynchronous _finalize_txn process so the worker isn't blocked on
PC commit, exposing true PC parallelism for disjoint addresses.
phyaddr.py documents the canonical bit layout (bits [10:8] for the
default burst=256, num_pcs=8 case). ADR-0033 D6 records the
derivation and the workload scenarios where address-striping
matters (strided streams, offset-disjoint parallel transfers).
Adds tests/test_hbm_address_based_pc.py: canonical bit mapping,
strided 8-way load distribution, same-address PC-0 serialization,
PC-aligned 2KB pair collision, dynamic pc_shift from burst_bytes,
and power-of-2 attr validation. Integration tests inspect
_pc_avail ledger directly: at default config UCIe's 8 ns per-txn
overhead exactly matches chunk_time, masking PC contention at the
makespan level even though the ledger correctly distinguishes the
cases.
Full suite: 631 passed, 1 skipped.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
99 lines
4.0 KiB
Python
99 lines
4.0 KiB
Python
from __future__ import annotations
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from collections.abc import Iterator
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from dataclasses import dataclass, field
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from typing import Any
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import simpy
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@dataclass
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class Transaction:
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"""In-flight request traversing the device fabric hop-by-hop (ADR-0015 D4).
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A Transaction carries a host request through one leg of the device fabric.
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Each component on the path reads from its in_port, processes (overhead_ns or
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other latency), and advances the Transaction to the next hop via out_port.
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Wire processes (ADR-0015 D2) model propagation delay between hops.
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Multi-leg flows (e.g. IO_CPU → M_CPU as leg 1, M_CPU.DMA → HBM as leg 2)
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use separate Transactions: the terminal component of leg 1 creates leg 2
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and waits for leg 2's done before succeeding leg 1's done.
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"""
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request: Any # original host request (MemoryReadMsg, KernelLaunchMsg, …)
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path: list[str] # node_id sequence for this leg
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step: int # index of the component currently holding this Transaction
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nbytes: int # payload size (bytes)
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done: simpy.Event # succeeded when this leg completes
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drain_ns: float = 0.0 # wormhole drain time: nbytes / bottleneck_bw (applied once at terminal)
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is_response: bool = False # True when carrying ResponseMsg on reverse path
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result_data: dict[str, Any] = field(default_factory=dict) # PE-level metrics (pe_exec_ns, etc.)
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base_address: int = 0 # HBM byte offset of the first chunk; per-flit addresses
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# derived as base + flit_index * flit_bytes (ADR-0033 D6)
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@property
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def next_hop(self) -> str | None:
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"""Node id of the next component, or None if this is the terminal hop."""
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nxt = self.step + 1
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return self.path[nxt] if nxt < len(self.path) else None
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def advance(self) -> Transaction:
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"""Return a copy of this Transaction advanced one step along the path."""
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return Transaction(
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request=self.request,
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path=self.path,
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step=self.step + 1,
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nbytes=self.nbytes,
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done=self.done,
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drain_ns=self.drain_ns,
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is_response=self.is_response,
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result_data=self.result_data,
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base_address=self.base_address,
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)
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def into_flits(self, flit_bytes: int) -> Iterator[Flit]:
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"""Decompose this Transaction's payload into Flits (ADR-0033 D1).
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Yields one Flit per ``flit_bytes`` of payload. The final flit may
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carry fewer bytes when ``nbytes`` is not a multiple of ``flit_bytes``;
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that flit has ``is_last=True``. Transactions with ``nbytes <= 0``
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yield no flits.
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All yielded Flits share a reference to this Transaction.
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"""
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if self.nbytes <= 0 or flit_bytes <= 0:
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return
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n_full = self.nbytes // flit_bytes
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remainder = self.nbytes % flit_bytes
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n_total = n_full + (1 if remainder else 0)
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for i in range(n_total):
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size = flit_bytes if i < n_full else remainder
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yield Flit(
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txn=self,
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flit_index=i,
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flit_nbytes=size,
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is_last=(i == n_total - 1),
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address=self.base_address + i * flit_bytes,
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)
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@dataclass
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class Flit:
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"""Atomic wire transport unit (ADR-0033 D1).
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Carries a slice of a parent Transaction's payload. The wire
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(``engine._wire``) decomposes Transactions into Flits on first
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transport; downstream wires pass Flits through with their own
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``bw_gbs`` delay.
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Phase 2 constraint: ``flit_bytes`` MUST be a multiple of HBM
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``burst_bytes`` (default they are equal). See ADR-0033 D1.
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"""
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txn: Transaction # parent transaction reference
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flit_index: int # 0..n_flits-1
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flit_nbytes: int # bytes carried (usually flit_bytes; last may be smaller)
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is_last: bool # True for the terminating flit
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address: int = 0 # HBM byte offset for this flit's chunk (ADR-0033 D6)
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