687c98086d
Filename + lifecycle:
- ADR rename to ADR-NNNN-<cat>-title.md with 8 3-letter category prefixes
(dev / mem / lat / prog / algo / par / api / ver). Numbers stay immutable.
- ADR Lifecycle split into 3 folders, documented in CLAUDE.md Part 2:
docs/adr/ (Accepted), docs/adr-proposed/ (Proposed/Stub/Draft),
docs/adr-history/ (Superseded/Merged). Status field gains "Draft" for
retroactive docs pending verification.
Merges (one ADR per topic, no change-history annotations):
- ADR-0017 absorbs ADR-0019 (Cube NOC + per-PE HBM connectivity, 10 D-items)
- ADR-0014 absorbs ADR-0021 (PE pipeline execution model, 8 D-items incl.
TileToken self-routing and multi-op composite epilogue scope)
- ADR-0023 absorbs docs/ipcq-dma-codesign-hw.md as new "HW Realization
Notes (Informative)" section (D16-D23 + Open HW Questions). codesign-hw.md
deleted; ADR-0019/0021 moved to adr-history with one-line stub status
Retroactive documentation (G4 closures, code-verified):
- ADR-0037 forwarding component (TransitComponent: first-flit overhead,
serial worker, path-based routing, single impl/multiple names)
- ADR-0036 IO_CPU component (target_start_ns global barrier stamping,
per-cube fan-out, response aggregation)
- ADR-0035 M_CPU & M_CPU.DMA component (3 fan-out paths, DMA Resources,
target_start_ns passthrough)
- ADR-0034 HBM controller internal design (per-PC state, address-based
selection, flit-aware per-flit commit, async finalize, command-only
fallback path)
Content updates:
- ADR-0010 expanded to full CLI surface (run/probe/web), retitled
"Command Line Interface and Execution Semantics"
- ADR-0007 D2 rewritten to current state; ADR-0015 supersession notes pruned
- ADR-0005 wrapped in Decision header with D1-D5; ADR-0022 metadata
block replaced with standard Status header
- ADR-0024 trimmed to rank=SIP launcher essentials (D1-D4);
ADR-0027 cleaned of supersession history
- ADR-0033 D6 cleanup: address-based PC selection moved out of future-work
(now documented in ADR-0034 D3); related D1/D3 wording realigned
- Cross-references back-filled in 5 ADRs (G3 gaps closed)
Onboarding docs split:
- docs/onboarding/ created
- moved: hw-architecture-overview.md, latency-model.md, di-presentation.md,
ccl-author-guide{,.en}.md
- references updated in README, ADR-0023{,.en}, src/kernbench/ccl/__init__.py
Source / test / yaml: ADR-NNNN cross-references in docstrings and YAML
comments updated after the merges (ADR-0021->0014 D6, ADR-0019->0017 D8).
No behavior change.
Tooling:
- tools/verify_adr_lang_pairs.py + tests/test_verify_adr_lang_pairs.py
(ADR EN/KO pair invariant checker)
- .claude/commands/report.md tracked (/report slash command)
- .gitignore: allow .claude/commands/*.md while keeping settings files ignored
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
3.2 KiB
3.2 KiB
ADR-0022: 2D Grid program_id Semantics
Status
Accepted
Context
Triton kernels use tl.program_id(axis) to identify their position in a launch grid.
Our hardware has a 2-level hierarchy: cubes contain PEs.
The previous implementation ignored the axis parameter and always returned a flat PE index,
making it impossible for kernels to distinguish their cube-local position from their cube identity.
Decision
Map tl.program_id and tl.num_programs to the 2D hardware grid:
| Call | Returns | Description |
|---|---|---|
tl.program_id(axis=0) |
local_pe_id |
PE index within cube |
tl.program_id(axis=1) |
cube_id |
Cube index |
tl.num_programs(axis=0) |
num_pes_per_cube |
PEs per cube |
tl.num_programs(axis=1) |
num_cubes |
Total cubes |
Global PID is derived as:
global_pid = tl.program_id(axis=1) * tl.num_programs(axis=0) + tl.program_id(axis=0)
Axis mapping rationale
- axis=0 = PE (innermost): PEs within a cube share HBM and communicate via local NOC mesh. This is the fast, tightly-coupled dimension — analogous to threads within a block.
- axis=1 = Cube (outer): Cross-cube communication goes through UCIe with higher latency. This is the coarser scheduling dimension — analogous to blocks in a grid.
Implementation
TLContext (triton_emu/tl_context.py)
Added cube_id and num_cubes constructor parameters. program_id() and num_programs() dispatch on axis:
def program_id(self, axis: int = 0) -> int:
if axis == 1:
return self._cube_id
return self._pe_id
def num_programs(self, axis: int = 0) -> int:
if axis == 1:
return self._num_cubes
return self._num_programs
PE_CPU (components/builtin/pe_cpu.py)
- Extracts
num_cubesfromctx.spec["system"]["sips"]["cubes_per_sip"] - Passes
cube_id(already available asself._cube_idx) andnum_cubesto TLContext
KernelRunner (triton_emu/kernel_runner.py)
- Receives
num_cubesfrom PE_CPU - Passes
cube_idandnum_cubesto TLContext in greenlet mode
Backward Compatibility
- Existing code using
tl.program_id(0)ortl.program_id()is unchanged — returns the same PE index as before. cube_idandnum_cubesdefault to0and1, so callers that don't provide them (e.g. unit tests) continue to work.
Usage Example
def sharded_gemm_kernel(a_ptr, b_ptr, out_ptr, M, K, N, tl):
local_pid = tl.program_id(axis=0) # PE within cube
cube_id = tl.program_id(axis=1) # which cube
global_pid = cube_id * tl.num_programs(axis=0) + local_pid
# Column-wise sharding across global PID
n_per_pid = N // (tl.num_programs(axis=1) * tl.num_programs(axis=0))
col_start = global_pid * n_per_pid
a = tl.load(a_ptr, shape=(M, K), dtype="f16")
b = tl.ref(b_ptr + col_start * K * 2, shape=(K, n_per_pid), dtype="f16")
h = tl.composite(op="gemm", a=a, b=b, out_ptr=out_ptr + col_start * M * 2)
tl.wait(h)
Consequences
- Benchmarks can now express cube-aware sharding and addressing without hardcoding topology dimensions.
- Future axis=2 (SIP-level) can be added following the same pattern if needed.