b6315c3c90
Two strands bundled as the 1H-codesign-paper refresh unit: (A) This session — single-op cost-model reflection (depends on2d8271c): - §2 Table 2 (tab:hw): split "FIXED per command" into "FIXED per single-op command" (8 cycles) and "FIXED per composite command" (40 cycles); §2 dispatch-overhead prose updated to the two-class split. - §3.4 (sec:gemm-vs-async): rename paragraph headers + prose to async-full / async-tiled; "atomic" -> "single-op" throughout; reframe mechanism #3 from the old DMA-only fast-path to the single-op fast-path. Headline narrative now: even with EVERY single-op cmd (96 DMA + 48 dot + 47 add) charged the light 8-cycle FIXED, composite still wins ~2.8x at K=3072 purely on command-count structure (1 vs 192 commands) -- down from the pre-D8 ~6.3x, and explicitly NOT a modelling artifact. Numbers refreshed from the regenerated sweep: async-full 3.83->3.91, async-tiled 1.14->~2.53, under-tile corner 1.06->1.21, depth-2 vs depth-inf spread <1%. New figure wired in. - build/main.pdf rebuilt (tectonic); pdftotext-verified (no broken refs; Table 2 split, single-op terms, 2.8x/2.53/192-host-commands all present). (B) Prior-session paper work riding along uncommitted: §4 all-reduce deep-edit, §5 GQA, §6 discussion trims; milestone_1h_ccl.py plot label "FSIM" -> "H2 2025 SW queue baseline"; regenerated diagrams under docs/diagrams/** and gemm output PNGs under 1H_milestone_output/gemm/. (Composite-window gemm plots are unaffected by D8 — D8 only changes single-op dispatch FIXED, which the composite window excludes.) All TODO items for the D8 single-op extension are now complete and pushed across 3 commits (2d8271ccost-model+ADR+tests,821bbf2bench harness, this paper refresh). Full regression green (826 passed, 1 skipped). No remaining work. NOTE for review (carried from2d8271c): ADR-0065's "2x CPU-offload win" headline for GQA decode opt2 may want a refresh to the post-D8 ~1.87x. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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| 1 | algorithm | sip_topology | n_sips | n_elem | bytes_per_pe | bytes_per_sip | latency_ns |
|---|---|---|---|---|---|---|---|
| 2 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 8 | 16 | 256 | 2918.5525000000157 |
| 3 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 32 | 64 | 1024 | 2999.740000000016 |
| 4 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 64 | 128 | 2048 | 3107.990000000019 |
| 5 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 128 | 256 | 4096 | 3324.4900000000207 |
| 6 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 512 | 1024 | 16384 | 3589.1133333333582 |
| 7 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 1024 | 2048 | 32768 | 3960.0333333333692 |
| 8 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 2048 | 4096 | 65536 | 4701.873333333393 |
| 9 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 4096 | 8192 | 131072 | 6185.020000000124 |
| 10 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 8192 | 16384 | 262144 | 9152.379999999861 |
| 11 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 16384 | 32768 | 524288 | 15087.099999999224 |
| 12 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 32768 | 65536 | 1048576 | 26956.540000000765 |
| 13 | lrab_hierarchical_allreduce | mesh_2d_no_wrap | 6 | 49152 | 98304 | 1572864 | 38825.97999999701 |
| 14 | lrab_hierarchical_allreduce | ring_1d | 6 | 8 | 16 | 256 | 2628.2558333333477 |
| 15 | lrab_hierarchical_allreduce | ring_1d | 6 | 32 | 64 | 1024 | 2699.943333333348 |
| 16 | lrab_hierarchical_allreduce | ring_1d | 6 | 64 | 128 | 2048 | 2795.526666666683 |
| 17 | lrab_hierarchical_allreduce | ring_1d | 6 | 128 | 256 | 4096 | 2986.693333333351 |
| 18 | lrab_hierarchical_allreduce | ring_1d | 6 | 512 | 1024 | 16384 | 3311.635000000021 |
| 19 | lrab_hierarchical_allreduce | ring_1d | 6 | 1024 | 2048 | 32768 | 3656.4016666666957 |
| 20 | lrab_hierarchical_allreduce | ring_1d | 6 | 2048 | 4096 | 65536 | 4345.401666666714 |
| 21 | lrab_hierarchical_allreduce | ring_1d | 6 | 4096 | 8192 | 131072 | 5721.801666666768 |
| 22 | lrab_hierarchical_allreduce | ring_1d | 6 | 8192 | 16384 | 262144 | 8479.934999999887 |
| 23 | lrab_hierarchical_allreduce | ring_1d | 6 | 16384 | 32768 | 524288 | 13996.201666665835 |
| 24 | lrab_hierarchical_allreduce | ring_1d | 6 | 32768 | 65536 | 1048576 | 25028.73500000064 |
| 25 | lrab_hierarchical_allreduce | ring_1d | 6 | 49152 | 98304 | 1572864 | 36061.26833333154 |
| 26 | lrab_hierarchical_allreduce | torus_2d | 6 | 8 | 16 | 256 | 1925.6025000000104 |
| 27 | lrab_hierarchical_allreduce | torus_2d | 6 | 32 | 64 | 1024 | 1978.290000000011 |
| 28 | lrab_hierarchical_allreduce | torus_2d | 6 | 64 | 128 | 2048 | 2048.540000000012 |
| 29 | lrab_hierarchical_allreduce | torus_2d | 6 | 128 | 256 | 4096 | 2189.040000000012 |
| 30 | lrab_hierarchical_allreduce | torus_2d | 6 | 512 | 1024 | 16384 | 2421.8183333333463 |
| 31 | lrab_hierarchical_allreduce | torus_2d | 6 | 1024 | 2048 | 32768 | 2702.2783333333473 |
| 32 | lrab_hierarchical_allreduce | torus_2d | 6 | 2048 | 4096 | 65536 | 3263.1983333333583 |
| 33 | lrab_hierarchical_allreduce | torus_2d | 6 | 4096 | 8192 | 131072 | 4384.5050000000665 |
| 34 | lrab_hierarchical_allreduce | torus_2d | 6 | 8192 | 16384 | 262144 | 6628.18500000005 |
| 35 | lrab_hierarchical_allreduce | torus_2d | 6 | 16384 | 32768 | 524288 | 11115.5449999995 |
| 36 | lrab_hierarchical_allreduce | torus_2d | 6 | 32768 | 65536 | 1048576 | 20090.265000000378 |
| 37 | lrab_hierarchical_allreduce | torus_2d | 6 | 49152 | 98304 | 1572864 | 29064.985000000597 |