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ywkang 687c98086d ADR housekeeping: category prefixes, lifecycle folders, retroactive 0034-0037

Filename + lifecycle:
- ADR rename to ADR-NNNN-<cat>-title.md with 8 3-letter category prefixes
  (dev / mem / lat / prog / algo / par / api / ver). Numbers stay immutable.
- ADR Lifecycle split into 3 folders, documented in CLAUDE.md Part 2:
  docs/adr/ (Accepted), docs/adr-proposed/ (Proposed/Stub/Draft),
  docs/adr-history/ (Superseded/Merged). Status field gains "Draft" for
  retroactive docs pending verification.

Merges (one ADR per topic, no change-history annotations):
- ADR-0017 absorbs ADR-0019 (Cube NOC + per-PE HBM connectivity, 10 D-items)
- ADR-0014 absorbs ADR-0021 (PE pipeline execution model, 8 D-items incl.
  TileToken self-routing and multi-op composite epilogue scope)
- ADR-0023 absorbs docs/ipcq-dma-codesign-hw.md as new "HW Realization
  Notes (Informative)" section (D16-D23 + Open HW Questions). codesign-hw.md
  deleted; ADR-0019/0021 moved to adr-history with one-line stub status

Retroactive documentation (G4 closures, code-verified):
- ADR-0037 forwarding component (TransitComponent: first-flit overhead,
  serial worker, path-based routing, single impl/multiple names)
- ADR-0036 IO_CPU component (target_start_ns global barrier stamping,
  per-cube fan-out, response aggregation)
- ADR-0035 M_CPU & M_CPU.DMA component (3 fan-out paths, DMA Resources,
  target_start_ns passthrough)
- ADR-0034 HBM controller internal design (per-PC state, address-based
  selection, flit-aware per-flit commit, async finalize, command-only
  fallback path)

Content updates:
- ADR-0010 expanded to full CLI surface (run/probe/web), retitled
  "Command Line Interface and Execution Semantics"
- ADR-0007 D2 rewritten to current state; ADR-0015 supersession notes pruned
- ADR-0005 wrapped in Decision header with D1-D5; ADR-0022 metadata
  block replaced with standard Status header
- ADR-0024 trimmed to rank=SIP launcher essentials (D1-D4);
  ADR-0027 cleaned of supersession history
- ADR-0033 D6 cleanup: address-based PC selection moved out of future-work
  (now documented in ADR-0034 D3); related D1/D3 wording realigned
- Cross-references back-filled in 5 ADRs (G3 gaps closed)

Onboarding docs split:
- docs/onboarding/ created
- moved: hw-architecture-overview.md, latency-model.md, di-presentation.md,
  ccl-author-guide{,.en}.md
- references updated in README, ADR-0023{,.en}, src/kernbench/ccl/__init__.py

Source / test / yaml: ADR-NNNN cross-references in docstrings and YAML
comments updated after the merges (ADR-0021->0014 D6, ADR-0019->0017 D8).
No behavior change.

Tooling:
- tools/verify_adr_lang_pairs.py + tests/test_verify_adr_lang_pairs.py
  (ADR EN/KO pair invariant checker)
- .claude/commands/report.md tracked (/report slash command)
- .gitignore: allow .claude/commands/*.md while keeping settings files ignored

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-05-20 01:15:55 -07:00

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ADR-0007: Runtime API and Simulation Engine Boundaries

Status

Accepted

Context

The simulator consists of multiple layers with distinct responsibilities:

a host-facing API layer used by benchmarks and user code,
a discrete-event simulation engine that executes requests,
device components that model hardware behavior.

Without strict boundaries, orchestration logic can leak into components, or simulation internals can become entangled with user-facing APIs.

This ADR defines clear responsibility boundaries between:

runtime API,
simulation engine (sim_engine),
hardware components.

Decision

D1. Runtime API is host-facing orchestration only

The runtime API represents host/driver-level behavior and MUST:

expose high-level operations (tensor deployment, kernel launch),
submit requests only to endpoint components (e.g., IO_CPU),
await completion via futures/handles,
own and persist host-side metadata (tensor allocation maps, kernel bindings).

The runtime API MUST NOT:

hardcode hop-by-hop routing or fan-out,
directly invoke internal components (M_CPU, PE_CPU, engines),
embed topology- or routing-specific assumptions.

D2. Simulation engine wires components and tracks completion

The simulation engine (sim_engine) MUST:

wire components at initialization (create port stores + start wire processes per the component port/wire framework — ADR-0015),
inject requests into the compiled topology graph at entry components (e.g., PCIE_EP for memory operations, IO_CPU for kernel launch),
schedule and execute events using a discrete-event model,
manage correlation ids and completion tracking.

The simulation engine MUST NOT:

define tensor semantics,
define kernel execution policies,
expose internal graph details to the runtime API,
walk the topology path during request execution,
call component run() methods directly,
track per-hop latency or decompose fan-out (components own this).

D3. Components own fan-out and aggregation

Device-side components MUST:

fan-out requests to downstream domains (IO_CPU → M_CPU → PE_CPU → schedulers/engines),
aggregate completion and failure signals,
propagate results deterministically upstream.

Neither the runtime API nor the simulation engine may orchestrate component-level fan-out explicitly.

Consequences

Runtime APIs remain stable as topology and routing evolve.
Simulation internals can change without affecting user-facing code.
Component implementations remain swappable via DI.

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