ywkang

ywkang pushed to master at ywkang/kernbench2

2026-05-19 18:42:53 +00:00

22fd0d2b9d ADR: introduce docs/history/, merge 0011+0018, prune migration cruft

ywkang pushed to master at ywkang/kernbench2

2026-05-18 19:08:16 +00:00

ecc57d050d CLAUDE.md: restructure into Part 1 (general) / Part 2 (project-specific)

ywkang pushed to master at ywkang/kernbench2

2026-05-15 16:43:12 +00:00

a76487ca48 PE_DMA perf: SIP-wide scenarios + dual outputs + clearer naming

ywkang pushed to master at ywkang/kernbench2

2026-05-15 15:53:02 +00:00

a143925a12 PE_DMA perf: dual-peak utilisation (single-path + aggregate)

ywkang pushed to master at ywkang/kernbench2

2026-05-15 14:59:45 +00:00

0bf220fed0 Switch PE_DMA perf plots to Effective BW utilization

ywkang pushed to master at ywkang/kernbench2

2026-05-15 08:23:43 +00:00

a759d58007 Add PE_DMA latency-breakdown plots + self-verification harness

ywkang pushed to master at ywkang/kernbench2

2026-05-15 08:04:35 +00:00

b8213d43a9 ADR-0019 D1/D4: per-PE HBM CTRL partitioning

ywkang pushed to master at ywkang/kernbench2

2026-05-15 07:18:51 +00:00

aaa1cbfaf6 ADR-0033 D6: address-based PC selection at HBM CTRL

ywkang pushed to master at ywkang/kernbench2

2026-05-15 06:24:03 +00:00

a44f832be5 Regenerate latency plots/diagrams for post-Phase-2c model

a0cccc71e8 Add HW architecture overview (Korean)

32b29a1e5c ADR-0003/0014: generalize "router mesh" to "NOC"

c9bd5387ac ADR-0033 D6: reorder future work by workload impact

Compare 4 commits »

ywkang pushed to master at ywkang/kernbench2

2026-05-15 06:20:14 +00:00

9beb140eaa ADR-0033 D6: clarify what multi-flow merging actually models

c6788788a4 ADR-0033 Phase 2c-3 finish: op_log test + ADR doc reflect chunk-streaming

6824a935c9 Calibrate 3 tests for ADR-0033 Phase 2c per-flit wire timing

4929040cf1 Phase 2c-2/3: per-flit wire timing + flit-aware routers + HBM CTRL

b31b3e8248 Phase 2c-1: wire chunkifies into Flits + reassembly compat layer

Compare 6 commits »

ywkang pushed to master at ywkang/kernbench2

2026-04-28 20:31:10 +00:00

533e699299 IPCQ-DMA co-design HW design doc + fix IPCQ slot BW model

ywkang pushed to master at ywkang/kernbench2

2026-04-28 04:25:46 +00:00

fca24feac5 Fix all remaining test failures: single-cube allreduce + matplotlib dep

ywkang pushed to master at ywkang/kernbench2

2026-04-28 00:15:03 +00:00

d55dc6cb4f Merge: accept remote pe2pe summary.csv

ywkang pushed to master at ywkang/kernbench2

2026-04-27 22:52:45 +00:00

81cc32c46b ADR-0001 Rev 2: 51-bit PhysAddr layout with concrete sub-unit tables

ywkang pushed to master at ywkang/kernbench2

2026-04-14 23:45:29 +00:00

cfc2d74ec4 Refactor ccl_allreduce bench: rank=SIP only, remove rank=PE legacy path

ywkang pushed to master at ywkang/kernbench2

2026-04-14 23:31:16 +00:00

105f1dc09e ADR-0027: Megatron TP API + worker-wait generalization + mp.spawn

ywkang pushed to master at ywkang/kernbench2

2026-04-14 21:13:27 +00:00

e7f376ebaa ADR-0027 rev7 (Megatron TP + worker-wait generalization) + ADR-0026 typo fix

ywkang pushed to master at ywkang/kernbench2

2026-04-14 20:02:27 +00:00

357cab525b ADR-0026: DPPolicy intra-device only + ShardSpec structural coords

ywkang pushed to master at ywkang/kernbench2

2026-04-14 19:46:39 +00:00

787409ced1 ADR-0024 Phase B: update xfail reason with architectural blocker details

ywkang pushed to master at ywkang/kernbench2

2026-04-14 16:14:05 +00:00

79124daab1 ADR-0024 Phase B (partial): scheduler-level collective drain