Reduce SRAM/UCIe/M_CPU/HBM node sizes, thin HBM and mesh links

Shrink cube-view component nodes to avoid clutter.
HBM and router_mesh edge lines made thinner and more transparent.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
2026-04-04 21:51:41 -07:00
parent f298e3c7cc
commit 5c6abe6d12
2 changed files with 166 additions and 153 deletions
+14 -1
View File
@@ -62,7 +62,12 @@ _KIND_SIZE: dict[str, tuple[float, float]] = {
"cube": (6.0, 4.0),
"iochiplet": (4.0, 1.5),
"switch": (5.0, 1.5),
"noc_router": (1.2, 0.8),
"noc_router": (1.0, 0.7),
"ucie_port": (1.2, 0.7),
"ucie_conn": (0.8, 0.5),
"sram": (1.4, 0.7),
"m_cpu": (1.4, 0.7),
"hbm_ctrl": (1.8, 0.8),
}
@@ -274,6 +279,14 @@ def _draw_edge(
color = _EDGE_COLORS.get(edge.kind, "#94a3b8")
width = "1.5" if edge.kind == "pe_internal" else "1"
opacity = "0.6" if edge.kind in ("command", "noc_to_ucie") else "0.8"
# HBM links: thin and faint to reduce clutter
if edge.kind in ("router_to_hbm", "hbm_to_router"):
width = "0.5"
opacity = "0.3"
# Router mesh links: thin
if edge.kind == "router_mesh":
width = "0.5"
opacity = "0.4"
if edge.kind in _FANOUT_KINDS and view.name == "cube":
# Orthogonal routing: src→horizontal→vertical→dst with per-edge offset.