ywkang
533e699299
Add hardware design document (docs/ipcq-dma-codesign-hw.md) covering PE_IPCQ high-level architecture, simulator verification, proposed HW implementation, and alternatives analysis. Include D2 block diagrams for baseline and proposed PE architectures. Fix IPCQ slot-memory bandwidth parameters to match topology.yaml: SRAM 128→512 GB/s (intrinsic BW, NoC-bottlenecked at 128), HBM 32→256 GB/s (was per-channel, now per-PE aggregate). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
122 lines
44 KiB
XML
122 lines
44 KiB
XML
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src: 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}
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.d2-713338305 .text-italic {
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font-family: "d2-713338305-font-italic";
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}
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@font-face {
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font-family: d2-713338305-font-italic;
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