ywkang
533e699299
Add hardware design document (docs/ipcq-dma-codesign-hw.md) covering PE_IPCQ high-level architecture, simulator verification, proposed HW implementation, and alternatives analysis. Include D2 block diagrams for baseline and proposed PE architectures. Fix IPCQ slot-memory bandwidth parameters to match topology.yaml: SRAM 128→512 GB/s (intrinsic BW, NoC-bottlenecked at 128), HBM 32→256 GB/s (was per-channel, now per-PE aggregate). Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
167 lines
3.3 KiB
Plaintext
167 lines
3.3 KiB
Plaintext
direction: right
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pe: PE {
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style.fill: "#f8f9fa"
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style.stroke: "#495057"
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style.border-radius: 8
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cpu: PE_CPU (control) {
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style.fill: "#bbdefb"
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style.stroke: "#1565c0"
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style.border-radius: 4
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}
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sched: PE_SCHED (dispatch) {
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style.fill: "#bbdefb"
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style.stroke: "#1565c0"
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style.border-radius: 4
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}
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ipcq: IPCQ Controller (NEW) {
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style.fill: "#e1f5fe"
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style.stroke: "#0277bd"
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style.border-radius: 6
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style.stroke-width: 2
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ptrmgmt: Pointer Mgmt {
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style.fill: "#b3e5fc"
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style.stroke: "#0277bd"
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style.border-radius: 4
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qprf: QPair Reg File
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bp: Backpressure
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sag: Slot Addr Gen
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}
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sideband: Sideband {
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style.fill: "#b3e5fc"
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style.stroke: "#0277bd"
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style.border-radius: 4
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metax: Meta Extractor
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crinj: Credit Injector
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crrcv: Credit Receiver
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}
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}
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dma: PE_DMA (MOD) {
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style.fill: "#fff3e0"
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style.stroke: "#e65100"
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style.border-radius: 6
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compute_port: compute port {
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style.fill: "#ffe0b2"
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style.stroke: "#e65100"
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style.border-radius: 4
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}
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ipcq_port: IPCQ port {
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style.fill: "#ffe0b2"
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style.stroke: "#e65100"
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style.border-radius: 4
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}
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wrr: WRR Arbiter (NEW) {
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style.fill: "#ffcc80"
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style.stroke: "#e65100"
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style.border-radius: 4
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style.stroke-width: 2
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}
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compute_port -> wrr
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ipcq_port -> wrr
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}
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fs: PE_FETCH_STORE {
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style.fill: "#c8e6c9"
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style.stroke: "#2e7d32"
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style.border-radius: 4
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}
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tcm: TCM (16MB SRAM) {
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style.fill: "#fce4ec"
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style.stroke: "#c62828"
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style.border-radius: 6
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work: Kernel Working Memory {
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style.fill: "#f8bbd0"
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style.stroke: "#c62828"
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style.border-radius: 4
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}
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slot: IPCQ Slot Region (rsv) {
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style.fill: "#f48fb1"
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style.stroke: "#c62828"
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style.border-radius: 4
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style.stroke-width: 2
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}
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}
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gemm: GEMM engine {
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style.fill: "#c8e6c9"
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style.stroke: "#2e7d32"
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style.border-radius: 4
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}
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math: MATH engine {
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style.fill: "#c8e6c9"
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style.stroke: "#2e7d32"
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style.border-radius: 4
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}
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fport: Fabric Port {
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style.fill: "#ffe0b2"
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style.stroke: "#e65100"
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style.border-radius: 4
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}
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# Control
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cpu -> sched: cmd dispatch
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cpu -> ipcq: MMIO
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# Compute pipeline
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sched -> dma.compute_port: TileToken
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dma -> fs: TileToken
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dma <-> tcm.work: DMA_READ/WRITE\n(HBM ↔ TCM)
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fs <-> tcm.work: fetch/store\n(TCM ↔ reg)
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fs -> gemm: TileToken
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fs -> math: TileToken
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gemm -> fs: TileToken
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math -> fs: TileToken
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# IPCQ data path
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ipcq -> dma.ipcq_port: IpcqDmaToken {style.stroke: "#0277bd"}
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dma -> ipcq.sideband.metax: IpcqMetaArrival {style.stroke: "#0277bd"}
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# IPCQ slot R/W
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dma <-> tcm.slot: slot read/write {
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style.stroke: "#0277bd"
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style.stroke-dash: 3
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}
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# Credit via fabric port
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ipcq.sideband.crinj -> fport: credit out (16B) {
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style.stroke: "#7b1fa2"
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style.stroke-dash: 5
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}
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fport -> ipcq.sideband.crrcv: credit in (16B) {
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style.stroke: "#7b1fa2"
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style.stroke-dash: 5
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}
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# DMA ↔ Fabric
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dma.wrr <-> fport
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}
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noc: NoC Router {
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style.fill: "#f3e5f5"
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style.stroke: "#6a1b9a"
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style.border-radius: 6
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}
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ext: Other PEs / Cubes / SIPs {
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style.fill: "#ede7f6"
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style.stroke: "#6a1b9a"
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style.border-radius: 6
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}
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pe.fport <-> noc
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noc <-> ext
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