ywkang
998cc85762
Major changes:
PE-level IPCQ infrastructure:
- New PE_IPCQ component: ring-buffer control plane with 4-direction
neighbor mapping, head/tail pointers, backpressure (poll/sleep).
- PE_DMA extended with vc_comm channel for IPCQ outbound/inbound DMA,
including in-flight data snapshot (D9) and op_log recording at
outbound time for Phase 2 replay correctness.
- IpcqDmaToken piggyback model: data + metadata travel together,
atomic visibility at receiver (invariant I6).
- Credit return fast path: bottleneck-BW latency, no fabric vc_comm.
Phase 2 data execution (ADR-0020 integration):
- op_log extended: DmaWriteCmd now captures src_space/src_addr for
Phase 2 dma_write copy; ipcq_copy ops recorded at outbound time.
- DataExecutor replays dma_write + ipcq_copy in t_start order.
- Engine._flush_data_phase: incremental cursor-based replay after
each engine.wait() so host reads see post-Phase-2 data.
- KernelRunner Phase 1 writes disabled when op_log is active to
prevent stale data from corrupting the MemoryStore snapshot.
TLContext / kernel API:
- tl.send(dir, src=TensorHandle), tl.recv(dir, shape, dtype),
tl.recv_async, tl.wait(RecvFuture), copy_to_dst mode.
- TensorHandle operator overloading (add/sub/mul/div) via thread-local
active TLContext → MathCmd dispatch through PE_MATH.
- PE-local scratch allocator for math output handles.
- tl.load returns space="hbm" handles for correct Phase 2 addressing.
- Additional math functions: maximum, minimum, fma, clamp, softmax, cdiv.
Unified ccl_allreduce bench (PyTorch-compat host code):
- Single benches/ccl_allreduce.py with run() + worker(rank, ws, torch)
split matching real PyTorch DDP worker pattern.
- torch.distributed facade: init_process_group, get_world_size,
get_rank, get_backend, all_reduce, barrier — only real PyTorch names.
- AhbmCCLBackend: eager install_ipcq at init, all_reduce dispatches
kernel via tensor shard metadata (n_elem from shards[0].nbytes).
- world_size derived from topology spec (sips × cubes × pes_per_cube)
with optional algorithm-level override in ccl.yaml.
Tensor API (PyTorch-compat surface):
- Tensor.numpy(): gather-aware (all shards via VA-based addressing).
- Tensor.copy_(source): scatter from host tensor into sharded target.
- RuntimeContext.from_numpy(arr): host-side staging tensor.
- Tensor.data property fixed to use numpy() (was shards[0]-only).
Algorithm modules moved to src/kernbench/ccl/algorithms/:
- ring_allreduce, mesh_allreduce, tree_allreduce, hello_send.
- Each module exports kernel_args(world_size, n_elem) helper.
- ccl.yaml module paths updated to kernbench.ccl.algorithms.*.
Dead code removed:
- 7 per-variant bench files (ccl_allreduce_{tcm,hbm,sram}, etc.).
- _run_ccl_bench greenlet-per-SIP scheduler.
- benches.loader.is_ccl_bench + run_rank detection.
- benches/ccl/ directory.
Tests:
- New test_ccl_allreduce_matrix.py: 7 parametrized cases
(ring×3 buffers, ring 8/16, mesh 4, tree 7).
- New test_runtime_api_tensor.py: copy_/numpy/from_numpy unit tests.
- Existing tests updated for new import paths + world_size_override.
Docs:
- Korean ccl-author-guide.md and ADR-0023 paths updated.
- New English versions: ccl-author-guide.en.md, ADR-0023.en.md.
502 tests pass.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
81 lines
2.9 KiB
Python
81 lines
2.9 KiB
Python
"""Tests for recv_mode='copy_to_dst' (ADR-0023 D9.5)."""
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from __future__ import annotations
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import numpy as np
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def test_recv_copy_to_dst_via_simpy_runner():
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"""Run a kernel that uses tl.recv(..., dst_addr=..., dst_space=...).
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Verify the data is moved to the dst location after recv.
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"""
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import importlib
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from kernbench.policy.placement.dp import DPPolicy
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from kernbench.runtime_api.bench_runner import run_bench
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from kernbench.runtime_api.types import resolve_device
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from kernbench.sim_engine.engine import GraphEngine
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from kernbench.topology.builder import resolve_topology
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from kernbench.common.pe_commands import TensorHandle
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def kernel(t_ptr, n_elem, dst_buf_addr, tl):
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rank = tl.program_id(axis=0)
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ws = tl.num_programs(axis=0)
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nbytes = n_elem * 2
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# Each PE sends own data, then recv into a custom dst slot
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current = TensorHandle(
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id="loc", addr=t_ptr + rank * nbytes,
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shape=(n_elem,), dtype="f16",
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nbytes=nbytes, data=None, space="hbm",
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)
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tl.send(dir="E", src=current)
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# copy_to_dst: move into a per-rank scratch HBM addr
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recv = tl.recv(
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dir="W", shape=(n_elem,), dtype="f16",
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dst_addr=dst_buf_addr + rank * nbytes,
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dst_space="hbm",
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)
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# Sanity: recv handle should now point to our dst addr
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assert recv.addr == dst_buf_addr + rank * nbytes
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assert recv.space == "hbm"
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topo = resolve_topology("topology.yaml")
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def run(torch):
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plan = torch.install_ipcq(
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algorithm="ring_allreduce_tcm", world_size_override=8,
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)
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a = torch.zeros(
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(1, 8 * 8),
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dtype="f16",
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dp=DPPolicy(
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sip="replicate", cube="replicate", pe="column_wise",
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num_sips=1, num_cubes=1,
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),
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name="copy_in",
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)
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store = torch.engine.memory_store
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base = a._handle.va_base or a._handle.shards[0].pa
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nbytes = 8 * 2
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for r in range(8):
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store.write("hbm", base + r * nbytes,
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np.full((8,), float(r + 1), dtype=np.float16))
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# Use a separate dst region (synthetic addresses)
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dst_buf = 0xC0FFEE_0000
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torch.launch("ring_allreduce_tcm", kernel, a, 8, dst_buf)
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# After the kernel, dst_buf + r*16 should contain rank (r-1)%8's data
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for r in range(8):
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arr = store.read("hbm", dst_buf + r * nbytes, shape=(8,), dtype="f16")
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expected = float(((r - 1) % 8) + 1)
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assert np.allclose(arr, expected), f"rank {r}: got {arr}, expected {expected}"
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result = run_bench(
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topology=topo, bench_fn=run,
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device=resolve_device("all"),
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engine_factory=lambda t, d: GraphEngine(
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getattr(t, "topology_obj", t), enable_data=True
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),
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)
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assert result.completion.ok
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