ywkang
22fd0d2b9d
- CLAUDE.md: add ADR Lifecycle subsection (superseded → docs/history/, immutable numbering, no renumber) - ADR-0011: merge ADR-0018 content as "Address Model: LA" section alongside PA / VA; status notes VA model is currently implemented - ADR-0018 / 0029 / 0031: moved to docs/history/ with status updates (0018 merged into 0011, 0029 superseded by 0032, 0031 absorbed into 0001 rev 2) - ADR-0019: rewrite Context as PE-HBM connectivity decision (self-contained, no LA model framing) - ADR-0019/0020/0021/0023/0025/0027: Status Proposed → Accepted (code verified) and prune Implementation Notes / Affected files / Test strategy / "현재 상태" sub-sections describing pre-impl state - ADR-0024/0026: same migration-flavor cleanup; 0026 also drops D6 Migration and D8 docs-update sub-decisions - ADR-0030: status simplified (blocker ADR-0031 now superseded) - SPEC.md: R10 + §0.2 reflect PA / VA / LA model names - ADR-0008/0012/0013: refresh ADR-0011 subtitle in Links 21 files changed, 553 insertions(+), 1290 deletions(-). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
101 lines
2.7 KiB
Markdown
101 lines
2.7 KiB
Markdown
# ADR-0008: Tensor Deployment and Allocation (Host Allocator, PA-first)
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## Status
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Accepted
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## Context
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Benchmarks require PyTorch-like tensor semantics:
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- tensor creation (empty, fill),
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- deployment to accelerator devices (tensor.to()).
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In the realistic system, host software manages allocation/mapping and installs
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mappings for DMA/MMU. For Phase 0 we simplify (ADR-0011):
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- device memory operations use PA only,
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- VA/MMU/IOMMU is not modeled.
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To keep the host↔device interface minimal, we avoid a separate
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AllocateTensorMeta message. Instead, host allocation produces a PA shard map
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that is used directly by MemoryWrite/Read and KernelLaunch.
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---
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## Decision
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### D1. Tensor is a host-owned handle with PA shard mapping
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A Tensor object is a host-owned handle that encapsulates:
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- shape and dtype,
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- initialization intent,
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- device placement and allocation metadata as a PA shard map.
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After deployment, the Tensor handle MUST contain:
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- a list of shards, each with (sip,cube,pe,pa,nbytes,offset_bytes).
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This PA shard mapping is the single source of truth for kernel argument binding.
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---
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### D2. Deployment uses a host allocator (Phase 0)
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In Phase 0, tensor deployment produces PA shard mappings via a host allocator:
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- placement (split/replicate/hybrid) is decided by a DP policy,
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- allocation assigns PA ranges at the PE level and returns shard mappings,
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- the Tensor handle stores the resulting shard list deterministically.
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No separate host-visible device allocation RPC is required in Phase 0.
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---
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### D3. Data initialization and transfer uses MemoryWrite/Read only
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Any data initialization or transfer implied by a tensor (e.g., fill, copy)
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MUST be represented using Host ↔ IO_CPU messages only:
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- MemoryWrite
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- MemoryRead
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Rules:
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- MemoryWrite/Read MUST reference PA + (sip,cube,pe) tags (ADR-0012).
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- Allocation metadata MUST NOT be embedded as a separate allocation message.
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- Bulk tensor data MUST NOT be embedded in Phase 0 messages.
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The simulation engine schedules MemoryWrite/Read through the graph so that
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latency is computed by explicit traversal.
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---
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### D4. Extension path (non-breaking)
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Future ADRs MAY introduce optional VA/MMU/IOMMU modeling by adding:
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- virtual addressing in tensor handles,
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- mapping install steps,
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- translation latency/page granularity.
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The Phase 0 PA shard map remains a valid fast-path configuration.
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---
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## Consequences
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- Host↔IO_CPU contract remains minimal (MemoryRead/Write + KernelLaunch).
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- KernelLaunch can pass per-PE data placement explicitly via shard tags.
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- Early implementation stays simple and testable.
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---
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## Links
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- ADR-0011 (Memory Addressing — PA / VA / LA)
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- ADR-0012 (Host↔IO_CPU schema)
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- ADR-0007 (runtime_api vs sim_engine boundaries)
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- ADR-0009 (Kernel execution)
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