ywkang
23992548f7
Three coupled fixes that recover small-tile GEMM pipeline efficiency from 53% to 88% (32x3072x32 load_ref, composite_window basis). 1. PE_DMA channel-hold (ADR-0014 D4 clarified): both the _handle_with_hooks (PeInternalTxn) and _pipeline_process (TileToken) paths used to hold the cap=1 DMA channel through the full HBM round-trip, which double-serialized with the HBM_CTRL's own per-PC `available_at` model and prevented back-to-back tile DMAs from amortizing their per-request head latency. Channel is now released after the request is enqueued onto the next hop; HBM serialization is HBM_CTRL's responsibility alone. Tests: new test_pe_dma_back_to_back_pipelining as the oracle (asserts wall < 75% of strict-serialized N x single_op). Existing test_pe_dma_record_start_after_channel_acquire rewritten to assert t_start clustering (channel released fast) instead of the old round-trip-hold invariant. test_pe_dma_same_channel_serializes still passes — HBM_CTRL preserves ordering. Probe regression: PE→local-HBM 32 KiB stays at 141 ns (single-request, unaffected). 2. milestone_1h_gemm bench: matmul_composite was reading MATMUL_M/K/N env vars at module load, so every sweep row replayed the cached 256³ result; values now read inside run(). Drops the stale sys.modules deletion hack. 3. Analytic ideal-pipeline model: dropped the (n_mn-1)·dma_w_per_pair penalty (over-pessimistic for under-tile shapes — it pushed measured > theoretical) and replaced the D_STAGES-derived head with empirical T_PIPELINE_FILL=60 ns / T_PIPELINE_TAIL=30 ns. Max analytic-vs-measured gap across all 7 swept shapes now 2.2 ppt (was 9-44 ppt under the old constants). Paper updates: - §3 (GEMM): 78%→88% measured at 48 tiles, 23%→15% at 1 tile, stage breakdown numbers refreshed (DMA in / Fetch / GEMM all ~785 ns at K=3072), analytic-vs-measured agreement tightened to "within 2.2 ppt". - §2.4 (Accuracy): GEMM tracking claim refreshed accordingly. - §5 (GQA): restore long-ctx 4-cases figures into figures/ (they were dropped from bench output dir as derived artifacts in92b9221/e45626cbut §5 still cites them by name). Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
112 lines
5.7 KiB
TeX
112 lines
5.7 KiB
TeX
\section{GEMM Acceleration via the Composite Command}
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\label{sec:gemm}
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GEMM is the compute core of every transformer block---the QKV
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projections, the attention score and context products, and the
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feed-forward matrices are all matrix multiplications. On a tiled
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accelerator a single logical GEMM expands into many hardware tiles, and
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each tile must be read from HBM, fetched into the register file, computed,
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stored, and written back. If every one of those tile-stage steps were an
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independently issued command, two costs would dominate. First, the host
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and the PE control processor would pay a per-command issue overhead
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$O(\text{tiles}\times\text{stages})$ times, which for a deep-$K$ reduction
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is hundreds to thousands of issues. Second, with stages dispatched
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one-at-a-time the scheduler cannot overlap the DMA of the next tile with
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the compute of the current one---the pipeline never fills, and the MAC
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array sits idle waiting for data. The hardware question is therefore: what
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issue mechanism lets a single GEMM saturate the MAC array without drowning
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in command overhead?
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\subsection{Design}
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The answer is the \emph{composite command}. A single command carries the
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ordered tile pipeline
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\[
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\textsf{DMA\_READ}\rightarrow\textsf{FETCH}\rightarrow\textsf{GEMM}
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\rightarrow\textsf{STORE}\rightarrow\textsf{DMA\_WRITE},
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\]
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and the PE scheduler splits the payload into hardware tiles
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(here $32\times64\times32$), emitting one tile token per tile. Subsequent
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stages are reached by \emph{token self-routing} between the on-PE engines,
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so a tile flows DMA\,$\rightarrow$\,fetch\,$\rightarrow$\,GEMM\,$%
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\rightarrow$\,store without returning to the scheduler between stages.
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Because the whole pipeline is described by one command, the issue cost is
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paid once per GEMM rather than once per tile-stage, and the scheduler is
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free to keep every stage busy on different tiles simultaneously---tile
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$i$'s GEMM overlaps tile $i{+}1$'s DMA read. A multi-operation composite
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additionally lets an epilogue (for example a vector-math step) ride the
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same tile loop, firing per $K$-tile, per output tile, or once per kernel
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according to its declared scope; this is what later allows an attention
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kernel to fuse its softmax work into the GEMM pipeline
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(\S\ref{sec:gqa}).
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\subsection{Results}
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We sweep eight GEMM shapes spanning square, tall, wide, and deep-$K$
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geometries, under three operand-staging variants
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(\textsf{ref\_ref}, both operands streamed from HBM; \textsf{load\_ref},
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one operand resident in TCM; \textsf{load\_load}, both resident).
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Figure~\ref{fig:gemm-util} reports MAC utilization and efficiency, and
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Figure~\ref{fig:gemm-stages} breaks the kernel into per-stage engine
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busy time.
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\begin{figure}[t]
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\centering
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\includegraphics[width=\linewidth]{gemm_mac_utilization_theoretical_vs_measured.png}
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\caption{GEMM MAC utilization and efficiency, theoretical vs.\ measured
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(\textsf{load\_ref} staging). Tile-fill sets the ceiling: under-tile
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shapes (marked $\ast$) such as $M{=}K{=}N{=}32$, $M{=}8$, and $K{=}8$
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cannot fill the MAC tile and cap at \SI{50}{\percent},
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\SI{25}{\percent}, \SI{12.5}{\percent}. For tile-filling shapes,
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efficiency climbs with tile count---from
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\textasciitilde\SI{15}{\percent} at one tile to \textasciitilde%
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\SI{88}{\percent} measured at 48 tiles ($K{=}3072$)---and the
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measured bars track the analytic ideal-pipeline prediction within
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\SI{2.2}{ppt} across every shape.}
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\label{fig:gemm-util}
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\end{figure}
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\begin{figure}[t]
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\centering
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\includegraphics[width=\linewidth]{gemm_stage_breakdown.png}
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\caption{Per-stage engine wall-clock (DMA in, Fetch, GEMM, DMA out)
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under \textsf{load\_ref} staging. For the deep-$K$ shape ($K{=}3072$,
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48 tiles) DMA in, Fetch, and GEMM are all close to
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\textasciitilde\SI{785}{\nano\second}, running concurrently in a
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tightly pipelined regime while DMA-out is negligible. For the
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low-reuse shape ($M{=}128,K{=}8,N{=}128$, 16 output tiles) DMA-out
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grows to \textasciitilde\SI{336}{\nano\second} while GEMM compute is
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\textasciitilde\SI{262}{\nano\second}---a data-movement-bound regime
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where the output write becomes the largest stage.}
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\label{fig:gemm-stages}
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\end{figure}
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Two regularities stand out. (i) Utilization is governed by how
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completely the problem fills the MAC tile: the three under-tile shapes
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are hard-capped well below \SI{100}{\percent}, independent of how the
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kernel is issued. (ii) Among tile-filling shapes, efficiency is
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governed by tile count---more tiles amortize the one-time pipeline
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fill, so the deep-$K$ shape reaches \textasciitilde\SI{88}{\percent}
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of peak while a single-tile shape reaches only
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\textasciitilde\SI{15}{\percent}. The stage breakdown explains why:
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with 48 tiles all three pipelined stages (DMA in, Fetch, GEMM) run
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concurrently at the per-tile bandwidth limit, whereas the low-reuse
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shape spends most of its time moving data in and out.
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\subsection{Analysis and meaning}
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The composite command does not manufacture bandwidth or MAC throughput; it
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removes the two software-shaped obstacles between a GEMM and its hardware
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roofline. By paying issue cost once per GEMM and chaining tile-stages
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through token self-routing, it lets the scheduler keep the pipeline full,
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so compute-rich shapes actually reach the efficiency their arithmetic
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intensity allows ($\sim$\SI{88}{\percent} measured at 48 tiles), and
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data-bound shapes actually reach their DMA bound instead of stalling on
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command overhead. The close agreement between measured and theoretical
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efficiency (Figure~\ref{fig:gemm-util}) is also the report's primary
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validation that KernBench's latency model is faithful in the regime that
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matters. The hardware implication is concrete: a single-command,
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self-routing tile pipeline is the issue mechanism that makes the MAC array
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usable, and it is a prerequisite---not a luxury---for the fused attention
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kernel of \S\ref{sec:gqa}.
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