ywkang
687c98086d
Filename + lifecycle:
- ADR rename to ADR-NNNN-<cat>-title.md with 8 3-letter category prefixes
(dev / mem / lat / prog / algo / par / api / ver). Numbers stay immutable.
- ADR Lifecycle split into 3 folders, documented in CLAUDE.md Part 2:
docs/adr/ (Accepted), docs/adr-proposed/ (Proposed/Stub/Draft),
docs/adr-history/ (Superseded/Merged). Status field gains "Draft" for
retroactive docs pending verification.
Merges (one ADR per topic, no change-history annotations):
- ADR-0017 absorbs ADR-0019 (Cube NOC + per-PE HBM connectivity, 10 D-items)
- ADR-0014 absorbs ADR-0021 (PE pipeline execution model, 8 D-items incl.
TileToken self-routing and multi-op composite epilogue scope)
- ADR-0023 absorbs docs/ipcq-dma-codesign-hw.md as new "HW Realization
Notes (Informative)" section (D16-D23 + Open HW Questions). codesign-hw.md
deleted; ADR-0019/0021 moved to adr-history with one-line stub status
Retroactive documentation (G4 closures, code-verified):
- ADR-0037 forwarding component (TransitComponent: first-flit overhead,
serial worker, path-based routing, single impl/multiple names)
- ADR-0036 IO_CPU component (target_start_ns global barrier stamping,
per-cube fan-out, response aggregation)
- ADR-0035 M_CPU & M_CPU.DMA component (3 fan-out paths, DMA Resources,
target_start_ns passthrough)
- ADR-0034 HBM controller internal design (per-PC state, address-based
selection, flit-aware per-flit commit, async finalize, command-only
fallback path)
Content updates:
- ADR-0010 expanded to full CLI surface (run/probe/web), retitled
"Command Line Interface and Execution Semantics"
- ADR-0007 D2 rewritten to current state; ADR-0015 supersession notes pruned
- ADR-0005 wrapped in Decision header with D1-D5; ADR-0022 metadata
block replaced with standard Status header
- ADR-0024 trimmed to rank=SIP launcher essentials (D1-D4);
ADR-0027 cleaned of supersession history
- ADR-0033 D6 cleanup: address-based PC selection moved out of future-work
(now documented in ADR-0034 D3); related D1/D3 wording realigned
- Cross-references back-filled in 5 ADRs (G3 gaps closed)
Onboarding docs split:
- docs/onboarding/ created
- moved: hw-architecture-overview.md, latency-model.md, di-presentation.md,
ccl-author-guide{,.en}.md
- references updated in README, ADR-0023{,.en}, src/kernbench/ccl/__init__.py
Source / test / yaml: ADR-NNNN cross-references in docstrings and YAML
comments updated after the merges (ADR-0021->0014 D6, ADR-0019->0017 D8).
No behavior change.
Tooling:
- tools/verify_adr_lang_pairs.py + tests/test_verify_adr_lang_pairs.py
(ADR EN/KO pair invariant checker)
- .claude/commands/report.md tracked (/report slash command)
- .gitignore: allow .claude/commands/*.md while keeping settings files ignored
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
77 lines
3.2 KiB
Markdown
77 lines
3.2 KiB
Markdown
# ADR-0004: Memory Semantics & Local-HBM Bandwidth Guarantee
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## Status
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Accepted
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## Context
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Accurately modeling PE↔HBM behavior is essential for kernel latency estimation.
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Each PE has a notion of “local HBM” that must guarantee full HBM bandwidth, independent of intervening on-die fabric bandwidth.
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## Decision
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### D1. Local HBM definition
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- Each PE is assigned a logically defined “local HBM” region.
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- Local HBM corresponds to the pseudo-channel subset directly attached to that PE’s
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router in the NOC mesh (ADR-0017 D4).
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- The path is: PE_DMA → local router → HBM_CTRL (switching overhead only, 0 mesh hops).
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- The mapping (HBM pseudo-channels → PE local regions) is derived from topology configuration.
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### D2. Local HBM bandwidth guarantee contract
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- Accesses from a PE to its local HBM MUST guarantee full effective HBM
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read/write bandwidth independent of intervening fabric bandwidth limits.
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- Effective HBM bandwidth = spec bandwidth x efficiency factor.
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The efficiency factor (configured via `hbm_ctrl.attrs.efficiency`, default 0.8)
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models real-world DRAM inefficiencies (refresh cycles, bank conflicts, page
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misses). For example: 256 GB/s spec x 0.8 = 204.8 GB/s effective.
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- The topology builder applies the efficiency factor to router-to-hbm edge
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bandwidth at graph construction time, so all downstream routing and latency
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computation uses the effective value.
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- This guarantee is modeled by:
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- a dedicated logical path and/or service model that enforces HBM BW at the PE-local-HBM interaction point,
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- while still incurring non-zero latency along explicitly modeled components.
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- HBM CTRL internal modeling (PC striping, cut-through, scheduling fidelity)
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is consolidated in ADR-0033 (Latency Model: Assumptions and Known
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Simplifications). The aggregate BW guarantee here remains the contract;
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ADR-0033 documents how the per-PC model realizes it and which scheduler
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effects are intentionally simplified.
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### D3. Remote PE HBM semantics (intra-cube)
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- A PE that accesses another PE's local HBM traverses the NOC:
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- PE_DMA → NOC → (fabric hops) → target PE's NOC port → HBM_CTRL
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- NOC bandwidth and hop count may limit remote HBM access relative to local access.
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### D4. Non-local HBM semantics (inter-cube / inter-SIP)
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- Accesses from a PE to HBM in a different cube or SIP MAY be limited by:
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- NOC bandwidth within the cube,
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- inter-cube UCIe links,
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- inter-SIP fabric (PCIe/UAL).
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- These paths MUST be explicit and traceable.
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### D5. Shared SRAM semantics
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- Each CUBE contains a shared SRAM accessible by all PEs in that CUBE.
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- Access path: PE_DMA → NOC → shared SRAM.
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- Shared SRAM bandwidth is limited by the NOC↔SRAM link bandwidth.
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- Shared SRAM is not part of the HBM address space; it is a separate memory domain.
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## Verification Notes
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Tests should cover:
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- local-HBM case: BW matches HBM BW regardless of fabric BW parameter
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- remote PE HBM case: latency includes mesh hop traversal
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- non-local cases (inter-cube/inter-SIP): BW/latency respond to fabric/link parameters
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- shared SRAM case: access via NOC with correct BW
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## Links
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- SPEC R2/R5
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- ADR-0002 (distance/order & explicit bypass)
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- ADR-0017 D7 (PE DMA data paths through NOC to HBM)
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