ywkang
5917b3497c
- Remove xbar_top/bot, bridge, single noc node from topology
- Each cube_mesh.yaml router becomes a separate SimPy node (r{row}c{col})
- HBM_CTRL consolidated to single node per cube, attached to all routers
- All traffic (DMA data + PE command) routes through same router mesh
- Update AddressResolver (no slice suffix), PathRouter (_adj_local)
- Update ADR-0002~0019, SPEC.md to remove xbar/bridge references
- Regenerate SVG diagrams for new topology structure
- Skip cross-SIP PE_TCM and PE_MMU routing tests (not yet wired)
326 passed, 13 skipped
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
72 lines
2.9 KiB
Markdown
72 lines
2.9 KiB
Markdown
# ADR-0004: Memory Semantics & Local-HBM Bandwidth Guarantee
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## Status
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Accepted
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## Context
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Accurately modeling PE↔HBM behavior is essential for kernel latency estimation.
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Each PE has a notion of “local HBM” that must guarantee full HBM bandwidth, independent of intervening on-die fabric bandwidth.
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## Decision
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### D1. Local HBM definition
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- Each PE is assigned a logically defined “local HBM” region.
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- Local HBM corresponds to the pseudo-channel subset directly attached to that PE’s
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router in the NOC mesh (ADR-0019).
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- The path is: PE_DMA → local router → HBM_CTRL (switching overhead only, 0 mesh hops).
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- The mapping (HBM pseudo-channels → PE local regions) is derived from topology configuration.
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### D2. Local HBM bandwidth guarantee contract
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- Accesses from a PE to its local HBM MUST guarantee full effective HBM
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read/write bandwidth independent of intervening fabric bandwidth limits.
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- Effective HBM bandwidth = spec bandwidth x efficiency factor.
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The efficiency factor (configured via `hbm_ctrl.attrs.efficiency`, default 0.8)
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models real-world DRAM inefficiencies (refresh cycles, bank conflicts, page
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misses). For example: 256 GB/s spec x 0.8 = 204.8 GB/s effective.
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- The topology builder applies the efficiency factor to router-to-hbm edge
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bandwidth at graph construction time, so all downstream routing and latency
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computation uses the effective value.
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- This guarantee is modeled by:
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- a dedicated logical path and/or service model that enforces HBM BW at the PE-local-HBM interaction point,
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- while still incurring non-zero latency along explicitly modeled components.
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### D3. Remote PE HBM semantics (intra-cube)
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- A PE that accesses another PE's local HBM traverses the router mesh:
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- PE_DMA → local router → (mesh hops) → target PE's router → HBM_CTRL
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- Router mesh bandwidth and hop count may limit remote HBM access relative to local access.
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### D4. Non-local HBM semantics (inter-cube / inter-SIP)
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- Accesses from a PE to HBM in a different cube or SIP MAY be limited by:
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- NOC bandwidth within the cube,
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- inter-cube UCIe links,
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- inter-SIP fabric (PCIe/UAL).
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- These paths MUST be explicit and traceable.
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### D5. Shared SRAM semantics
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- Each CUBE contains a shared SRAM accessible by all PEs in that CUBE.
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- Access path: PE_DMA → NOC → shared SRAM.
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- Shared SRAM bandwidth is limited by the NOC↔SRAM link bandwidth.
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- Shared SRAM is not part of the HBM address space; it is a separate memory domain.
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## Verification Notes
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Tests should cover:
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- local-HBM case: BW matches HBM BW regardless of fabric BW parameter
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- remote PE HBM case: latency includes mesh hop traversal
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- non-local cases (inter-cube/inter-SIP): BW/latency respond to fabric/link parameters
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- shared SRAM case: access via NOC with correct BW
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## Links
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- SPEC R2/R5
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- ADR-0002 (distance/order & explicit bypass)
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- ADR-0017 D7 (PE DMA data paths through NOC to HBM)
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