ywkang
5fdb6f8797
Previous model double-counted slow-upstream paths (e.g., 64KB via UCIe 128 GB/s was ~2x pessimistic). HBM CTRL now distributes bursts across 8 pseudo-channels via global round-robin, with per-chunk commit timing that pipelines correctly against the bottleneck link's data arrival. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
100 lines
4.6 KiB
Markdown
100 lines
4.6 KiB
Markdown
# ADR-0033 — Latency Model: Assumptions and Known Simplifications
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## Status
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Accepted
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## Context
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The simulator is an analytical, event-driven performance model — not a
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cycle-accurate or RTL-level simulator. Many real-HW effects are approximated
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or omitted by design. To keep the model auditable and reviewable as a whole,
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this ADR consolidates the assumptions in one place. Individual component ADRs
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(ADR-0015, ADR-0019, ADR-0004) define the *mechanisms*; this document defines
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the *limits of fidelity*.
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## Decisions
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### D1. Modeled precisely
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- **Per-directed-edge BW occupancy** (FIFO serialization via `available_at`) —
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ADR-0015 D2.
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- **Per-component switching/overhead latency** (`overhead_ns` attr).
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- **HBM per-pseudo-channel parallelism** via stateless `pc_avail[N]` array
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with global round-robin chunking. Burst granularity tunable
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(`burst_bytes`, default 256B). Read and write share each PC's
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`available_at` (real HW command bus is per-PC shared).
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- **HBM direction switching penalty mechanism**: per-PC last-direction
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tracking + configurable `switch_penalty_ns`. Default 0 — see D2.
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- **Wire cut-through at HBM CTRL**: PC chunk scheduling starts at virtual
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head-arrival time `env.now - txn.drain_ns`, allowing PC commit to overlap
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with wire transfer that has already elapsed. The cut-through is local to
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HBM CTRL (no Transaction-level head event, no wire-level change); ADR-0015
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wire semantics are preserved.
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### D2. Approximated (with known directional error)
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| Effect | Real HW | Our model | Error direction |
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|--------|---------|-----------|----------------|
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| Router output port arbitration | Round-robin / weighted | Wire edge FIFO | HoL blocking exaggerated; fairness not modeled |
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| Multi-flow BW sharing | Per-flow fair share | FIFO atomic occupancy | Per-txn latency dist. differs; makespan correct |
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| HBM scheduler / write buffer | FR-FCFS + watermark drain | FIFO, no reordering | Switching penalty over-charged when alternations are dense — but default `switch_penalty_ns = 0` assumes ideal scheduler amortizes it (Tier 0) |
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| Flit/cycle granularity | Discrete flits @ cycle rate | Continuous nbytes | Sub-flit small-message noise |
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| Wire cut-through scope | Wormhole at every hop | Cut-through absorbed at HBM CTRL only | Intermediate hops still store-and-forward semantics; acceptable because component overheads at intermediate nodes are size-independent |
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### D3. Ignored (out of scope)
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- Bank-level row buffer conflict penalty (assume no conflicts — best case;
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round-robin chunk assignment is address-blind so we cannot detect same-bank
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reuse).
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- HBM tRP / tRCD / tFAW / tRC timing constraints (absorbed into the steady-state
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`burst_time = burst_bytes / pc_bw_gbs`).
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- Refresh, ECC, thermal throttling, power gating.
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- Clock domain crossings, PLL lock time.
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- Flit-level discrete interleaving on links.
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- Upstream backpressure due to downstream buffer occupancy (input ports use
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unbounded `simpy.Store`).
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### D4. Workload sensitivity
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Workloads where the above simplifications meaningfully affect results:
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- **Random scatter/gather**: bank conflict ignored → model optimistic.
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- **Heavy mixed R/W intensive** (e.g., GEMM bias accumulation): HBM scheduler
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absent. With default `switch_penalty_ns = 0` we assume ideal amortization;
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setting it non-zero models pessimistic per-alternation cost.
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- **High concurrency (>10 active flows on one link)**: HoL blocking and VC
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limits not modeled → model optimistic.
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- **Very small (sub-flit) transactions**: flit quantization noise.
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### D5. Verification policy
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For workloads in D4, cross-check against real HW or a cycle-accurate
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simulator before drawing absolute-magnitude conclusions. The model remains
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accurate for **relative comparisons** within the modeled regime.
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### D6. Future work
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- [ ] Bank-level conflict modeling (opt-in via `track_banks: true`).
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- [ ] HBM scheduler with write buffer + watermark drain (Tier 2 from the
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design discussion).
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- [ ] Fluid wire model for multi-flow router contention.
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- [ ] Wire-level cut-through at intermediate routers (currently destination
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HBM CTRL only).
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- [ ] Backpressure modeling for finite component buffers.
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## Consequences
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- Single review point for all model fidelity questions. Each future PR
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touching latency must update the relevant section here.
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- Workload-specific magnitude error envelopes are explicit.
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- Builder-side derivation of `pc_bw_gbs = hbm_to_router_bw_gbs / num_pcs`
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enforces the ADR-0019 D9 invariant in code rather than relying on yaml
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manual consistency.
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## Cross-references
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- ADR-0015 — component / port / wire model.
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- ADR-0019 — NoC and local HBM topology.
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- ADR-0004 — memory semantics, local HBM.
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